Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 6-39. McBSP1,2,4,5 Output Clock Pulse Duration (continued)
PARAMETER VDDSHV = 1.8V, 3.3V UNIT
tW(CLKL) Typical pulse duration, 0.5*P
(2)
0.5*P
(2)
ns
mcbsp1_clkr /
mcbspx_clkx low
(1)
tdc(CLK) Duty cycle error, -0.75 0.75 ns
mcbsp1_clkr /
mcbspx_clkx
(1)
Table 6-40. McBSP3 Output Clock Pulse Duration
PARAMETER VDDSHV = 1.8V, 3.3V UNIT
MIN MAX
tC(CLK) Cycle time, mcbsp3_clkx 31.25 ns
tW(CLKH) Typical pulse duration, 0.5*P
(1)
0.5*P
(1)
ns
mcbsp3_clkx high
tW(CLKL) Typical pulse duration, 0.5*P
(1)
0.5*P
(1)
ns
mcbsp3_clkx low
tdc(CLK) Duty cycle error, -0.75 0.75 ns
mcbsp3_clkx
(1) P = mcbsp3_clkx clock period
6.6.1.1.1 McBSP1
The following tables show the timing requirements and switching characteristics for McBSP1.
Table 6-41. McBSP1 Timing Requirements - Rising Edge and Receive Mode
No. PARAMETER VDDSHV=3.3V VDDSHV=1.8V UNIT
MIN MAX MIN MAX
B3 tsu(DRV- Setup time, Half Cycle 5.0 5.0 ns
CLKAE) mcbsp1_dr Master
valid before
Half Cycle 5.2 5.2 ns
mcbsp1_clkr /
Slave
mcbsp1_clkx
active edge
Full Cycle 4.0 4.0 ns
Master
Full Cycle 4.2 4.2 ns
Slave
B4 th(CLKAE- Hold time, Half Cycle 5.8 5.8 ns
DRV) mcbsp1_dr Master
valid after
Half Cycle 5.2 5.2 ns
mcbsp1_clkr /
Slave
mcbsp1_clkx
active edge
Full Cycle 1.5 1.5 ns
Master
Full Cycle 0.9 0.9 ns
Slave
B5 tsu(FSV- Setup time, Half Cycle 5.2 5.2 ns
CLKAE) mcbsp1_fsr / Slave
mcbsp1_fsx
Full Cycle 4.2 4.2 ns
valid before
Slave
mcbsp1_clkr /
mcbsp1_clkx
active edge
B6 th(CLKAE-FSV) Hold time, Half Cycle 0.5 0.5 ns
mcbsp1_fsr / Slave
mcbsp1_fsx
Full Cycle 1.0 1.0 ns
valid after
Slave
mcbsp1_clkr /
mcbsp1_clkx
active edge
156 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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