Datasheet

dss_pclk
dss_vsync
dss_hsync
dss_acbias
dss_data[23:0]
DL4
DL5
DL3
030-062
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
6.5.2.1.2 LCD Display in STN Mode
Table 6-37 assumes testing over the recommended operating conditions (see Figure 6-36).
Table 6-37. LCD Display Interface Switching Characteristics in STN Mode
(1) (2) (3)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
DL3 t
d(PCLKA-DATAV)
Delay time, dss_pclk active edge to dss_data bus valid -4.21 6.9 ns
DL4 t
c(PCLK)
Cycle time
(4)
, dss_pclk 22.73 ns
DL5 t
w(PCLK)
Pulse duration, dss_pclk low or high 10.23 12.5 ns
c
load
Load capacitance 40 pF
(1) The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low.
(2) The capacitive load is equivalent to 40 pF.
(3) For more information, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0).
(4) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the
DISPC_DIVISOR register.
Figure 6-36. LCD Display in STN Mode(1) (2) (3) (4) (5)
(1) The pixel data bus depends on the use 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins.
(2) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.
(3) dss_vsync width must be programmed to be as small as possible.
(4) The pixel clock frequency is programmable.
(5) For more information, see the AM35x ARM Microprocessor Technical Reference Manual (literature number SPRUGR0).
154 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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