Datasheet
VF1
VDIN_CLK
(Falling Edge)
VF2
VF7
VF7
VF10
VF8, VF9, VF11
VF3, VF4, VF6
VF5
VDIN_CLK
(Rising Edge)
VDIN_D[xx]
VDIN_HD,
VDIN_VD,
VDIN_FIELD
VDIN_WEN
SPRS550-001
AM3517, AM3505
www.ti.com
SPRS550E –OCTOBER 2009–REVISED MARCH 2013
6.5.1.1.1 Video Processing Front End (VPFE) Timing
The following tables assume testing over recommended operating conditions.
Table 6-34. VPFE Timing Requirements
1.8V, 3.3V
NO. PARAMETER
MIN MAX UNIT
VF1 t
c(VDIN_CLK)
Cycle time, pixel clock input, VDIN_CLK 13.33 100 ns
VF2 t
su(VDIN_D-VDIN_CLK)
Setup time, VDIN_D to VDIN_CLK rising edge 3.5 ns
VF3 t
su(VDIN_HD-VDIN_CLK)
Setup time, VDIN_HD to VDIN_CLK rising edge 3.5 ns
VF4 t
su(VDIN_VD-VDIN_CLK)
Setup time, VDIN_VD to VDIN_CLK rising edge 3.5 ns
VF5 t
su(VDIN_WEN-VDIN_CLK)
Setup time, VDIN_WEN to VDIN_CLK rising edge 3.5 ns
VF6 t
su(C_FLD-VDIN_CLK)
Setup time, VDIN_FIELD to VDIN_CLK rising edge 3.5 ns
VF7 t
h(VDIN_CLK-VDIN_D)
Hold time, VDIN_D valid after VDIN_CLK rising edge 2.5 ns
VF8 t
h(VDIN-HD-VDIN_CLK)
Hold time, VDIN_HD to VDIN_CLK rising edge 2.5 ns
VF9 t
h(VDIN_VD-VDIN_CLK)
Hold time, VDIN_VD to VDIN_CLK rising edge 2.5 ns
VF10 t
h(VDIN_WEN-VDIN_CLK)
Hold time, VDIN_WEN to VDIN_CLK rising edge 2.5 ns
VF11 t
h(C_FLD-VDIN_CLK)
Hold time, VDIN_FIELD to VDIN_CLK rising edge 2.5 ns
Table 6-35. VPFE Output Switching Characteristics
1.8V, 3.3V
NO. PARAMETER
MIN MAX UNIT
VF12 t
d(VDIN_HD-VDIN_CLK)
Output delay time, VDIN_HD to CLK rising edge 10 ns
VF13 t
d(VDIN_VD-VDIN_CLK)
Output delay time, VDIN_VD to CLK rising edge 10 ns
VF14 t
d(VDIN_WEN-VDIN_CLK)
Output delay time, VDIN_WEN to CLK rising edge 10 ns
VF15 t
oh(VDIN_HD-VDIN_CLK)
Output hold time, VDIN_HD to CLK rising edge 0.5 ns
VF16 t
oh(VDIN_VD-VDIN_CLK)
Output hold time, VDIN_VD to CLK rising edge 0.5 ns
VF17 t
oh(C_FLD-VDIN_CLK)
Output hold time, VDIN_FLD to CLK rising edge 0.5 ns
Figure 6-32. VPFE0 Input Timings
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 151
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