Datasheet

A1
A1
T
T
FL
FH
DDR2
Controller
Microprocessor
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 6-32. DQS and Dx Routing Specification
(1) (2)
No. Parameter Min Typ Max Unit Notes
1 Center to center DQS-DQSN spacing 2w
2 DQS E differential pair Skew Length Mismatch
(3)
25 Mils
3 Center to center DQS to other DDR2 trace spacing 4w See Note
(4)
4 DQS/Dx nominal trace length DQLM-50 DQLM DQLM+ Mils See Notes
(2)
,
50
(5)
5 Dx to DQS Skew Length Mismatch 100 Mils See Note
(5)
6 Dx to Dx Skew Length Mismatch 100 Mils See Note
(5)
7 Center to center Dx to other DDR2 trace spacing 4w See Notes
(4)
,
(6)
8 Center to Center Dx to other Dx trace spacing 3w See Notes
(7)
,
(4)
(1) "Dx" indicates a data line. E indicates length of DQS differential pair or Dx signal.
(2) Series terminator, if used, should be located closest to DDR.
(3) Differential impedance should be 100-ohms.
(4) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(5) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte
1.
(6) Dx's from other DQS domains are considered other DDR2 trace.
(7) DQLM is the longest Manhattan distance of each of the DQS and Dx net classes.
Figure 6-30 shows the routing for the SDRC_STRBENx net classes. Table 6-33 contains the routing
specification. SDRC_STRBENx net classes should be shielded from or routed on different layers than the
DQx net classes.
Figure 6-30. SDRC_STRBENx Routing
148 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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