Datasheet

A1
A1
C B
A
T
DDR2
Controller
Microprocessor
Microprocessor
A1
A1
DDR2 Device
VREF Nominal Minimum
Trace Width is 20 Mils
VREF Bypass Capacitor
Neck down to minimum in BGA escape
regions is acceptable. Narrowing to
accomodate via congestion for short
distances is also acceptable. Best
performance is obtained if the width
of VREF is maximized.
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
6.4.2.2.10 VREF Routing
VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM3517/05. VREF
is intended to be half of the DDR2 power supply voltage and should be created using a resistive divider as
shown in Figure 6-23. Other methods of creating VREF are not recommended. Figure 6-27 shows the
layout guidelines for VREF.
Figure 6-27. VREF Routing and Topology
6.4.2.2.11 DDR2 CLK and ADDR_CTRL Routing
Figure 6-28 shows the topology of the routing for the CLK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
Figure 6-28. CLK and ADDR_CTRL Routing and Topology
146 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM3517 AM3505