Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 6-28. Clock Net Class Definitions
Clock Net Class AM3517/05 Device Pin Names
CK sdrc_clk/sdrc_nclk
DQS0 sdrc_dqs0p /sdrc_dqs0n
DQS1 sdrc_dqs1p /sdrc_dqs1n
DQS2 sdrc_dqs2p/sdrc_dqs2n
DQS3 sdrc_dqs3p/sdrc_dqs3n
Table 6-29. Signal Net Class Definitions
Associated Clock Net
Clock Net Class Class AM3517/05 Device Pin Names
ADDR_CTRL CK sdrc_ba[2:0], sdrc_ncs1, sdrc_a[14:0], sdrc_ncs0 , sdrc_ncas, sdrc_nras,
sdrc_nwe, sdrc_cke0
DQ0 DQS0 sdrc_d[7:0], sdrc_dm0
DQ1 DQS1 sdrc_d[15:8], sdrc_dm1
DQ2 DQS2 sdrc_d[23:16],sdrc_dm2
DQ3 DQS3 sdrc_d[31:24],sdrc_dm3
SDRC_STRBEN0 CK,DQS0,DQS1 sdrc_strben0, sdrc_strben_dly0
SDRC_STRBEN1 CK,DQS2,DQS3 sdrc_strben1, sdrc_strben_dly1
6.4.2.2.9 DDR2 Signal Termination
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only
type permitted. Table 6-30 shows the specifications for the series terminators.
Table 6-30. DDR2 Signal Terminations
No. Parameter Min Typ Max Unit Notes
1 CLK Net Class 0 10 Ω See Note
(1)
2 ADDR_CTRL Net Class 0 22 Zo Ω See Notes
(1)
,
(2)
,
(3)
3 Data Byte Net Classes (DQS0-DQS1, D0-D31) 0 22 Zo Ω See Notes
(1)
,
(2)
,
(3)
4 SDRC_STRBENx Net Class (SDRC_STRBENx) 0 10 Zo Ω See Notes
(1)
,
(2)
,
(3)
(1) Only series termination is permitted, parallel or SST specifically disallowed.
(2) Terminator values larger than typical only recommended to address EMI issues.
(3) Termination value should be uniform across net class.
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 145
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