Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
6.4.2.2.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass cap, AM3517/05 DDR2 power, and
AM3517/05 DDR2 ground connections. Table 6-27 contains the specification for the HS bypass capacitors
as well as for the power connections on the PCB.
6.4.2.2.8 Net Classes
Table 6-28 lists the clock net classes for the DDR2 interface. Table 6-29 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 6-27. High-Speed Bypass Capacitors
No. Parameter Min Max Unit Notes
1 HS Bypass Capacitor Package Size 0402 10 Mils See Note
(1)
2 Distance from HS bypass capacitor to device being bypassed 250 Mils
3 Number of connection vias for each HS bypass capacitor 2 Vias See Note
(2)
4 Trace length from bypass capacitor contact to connection via 1 30 Mils
5 Number of connection vias for each DDR2 device power or ground balls 1 Vias
6 Trace length from DDR2 device power ball to connection via 35 Mils
7 VDDS HS Bypass Capacitor Count 20 Devices See Note
(3)
8 VDDS HS Bypass Capacitor Total Capacitance 1.2 μF
9 DDR#1 HS Bypass Capacitor Count 8 Devices See Note
(3)
10 DDR#1 HS Bypass Capacitor Total Capacitance 0.4 μF
11 DDR#2 HS Bypass Capacitor Count 8 Devices See Notes
(3)
,
(4)
12 DDR#2 HS Bypass Capacitor Total Capacitance 0.4 μF See Note
(4)
(1) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Only used on dual-memory systems
144 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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