Datasheet

A1
A1
DDR2
Controller
DDR2
Device
Region should encompass all DDR2 circuitry and varies depending
on placement. Non-DDR2 signals should not be routed on the DDR
signal layers within the DDR2 keep out region. Non-DDR2 signals may
be routed in the region provided they are routed on layers separated
from DDR2 signal layers by a ground layer. No breaks should be
allowed in the reference ground layers in this region. In addition, the
1.8 V power plane should cover the entire keep out region.
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Table 6-25. Placement Specifications
No. Parameter Min Max Unit Notes
1 X 1750 Mils See Notes
(1)
,
(2)
2 Y 1280 Mils See Notes
(1)
,
(2)
3 Y Offset 650 Mils See Notes
(1)
.
(2)
,
(3)
4 DDR2 Keepout Region See Note
(4)
5 Clearance from non-DDR2 signal to DDR2 Keepout Region 4 w See Note
(5)
(1) See Figure 6-23 for dimension definitions.
(2) Measurements from center of AM3517/05 device to center of DDR2 device.
(3) For single memory systems it is recommended that Y Offset be as small as possible.
(4) DDR2 Keepout region to encompass entire DDR2 routing area
(5) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.
6.4.2.2.5 DDR2 Keep Out Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keep
out region is defined for this purpose and is shown in Figure 6-26. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keep out region are shown in Table 6-
25.
Figure 6-26. DDR2 Keepout Region
142 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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