Datasheet

GPMC_FCLK
gpmc_clk
gpmc_ncsx
gpmc_a[26:17]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_a[16:1]_d[15:0]
gpmc_io_dir
gpmc_waitx
Address(MSB)
Valid
Valid
Address(LSB)
DataIN DataIN
OUT IN
OUT
FA0
FA9
FA10
FA3
FA13
FA29
FA1
FA37
FA12
FA4
FA10
FA0
FA5
030-030
FA15
FA14
AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Figure 6-11. GPMC/Multiplexed NOR Flash – Asynchronous Read – Single Word Timing(1) (2) (3)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.
FA5 value must be stored inside AccessTime register bit field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 123
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