Datasheet

GPMC_FCLK
gpmc_clk
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_noe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Address0 Address1
Valid Valid
Valid Valid
DataUpper
OUTOUT IN OUT IN
FA9
FA10
FA3
FA9
FA3
FA13 FA13
FA1 FA1
FA4 FA4
FA12 FA12
FA10
FA0 FA0
FA16
FA0 FA0
FA10 FA10
FA5 FA5
030-027
FA15
FA15
FA14
FA14
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Figure 6-8. GPMC/NOR Flash – Asynchronous Read – 32-bit Timing(1) (2) (3)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.
FA5 value must be stored inside AccessTime register bit field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
120 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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