Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
F0 t
c(CLK)
Cycle time
(1)
, output clock gpmc_clk 10 ns
period
F1 t
w(CLKH)
Typical pulse duration, output clock 0.5 P
(2)
0.5 P
(2)
ns
gpmc_clk high
F1 t
w(CLKL)
Typical pulse duration, output clock 0.5 P
(2)
0.5 P
(2)
ns
gpmc_clk low
t
dc(CLK)
Duty cycle error, output clk gpmc_clk -500 500 ps
t
j(CLK)
Jitter standard deviation
(3)
, output clock 33.30 ps
gpmc_clk
t
R(CLK)
Rise time, output clock gpmc_clk 1.6 ns
t
F(CLK)
Fall time, output clock gpmc_clk 1.6 ns
t
R(DO)
Rise time, output data 2 ns
t
F(DO)
Fall time, output data 2 ns
F2 t
d(CLKH-nCSV)
Delay time, gpmc_clk rising edge to F
(5)
- 1.9 F
(5)
+ 3.3 ns
gpmc_ncsx
(4)
transition
F3 t
d(CLKH-nCSIV)
Delay time, gpmc_clk rising edge to E
(6)
- 1.9 E
(6)
+ 3.3 ns
gpmc_ncsx
(4)
invalid
F4 t
d(ADDV-CLK)
Delay time, address bus valid to B
(7)
- 4.1 B
(7)
+ 2.1 ns
gpmc_clk first edge
F5 t
d(CLKH-ADDIV)
Delay time, gpmc_clk rising edge to -2.103 ns
gpmc_a[16:1] invalid
F6 t
d(nBEV-CLK)
Delay time, gpmc_nbe0_cle, gpmc_nbe1 B
(7)
- 1.37 B
(7)
+ 2.1 ns
valid to gpmc_clk first edge
F7 t
d(CLKH-nBEIV)
Delay time, gpmc_clk rising edge to D
(8)
- 2.1 D
(8)
+ 1.1 ns
gpmc_nbe0_cle, gpmc_nbe1 invalid
(1) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the I/F module by setting the
GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.
(2) P = gpmc_clk period
(3) The jitter probability density can be approximated by a Gaussian function.
(4) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(5) For nCS falling edge (CS activated):
• Case GpmcFCLKDivider = 0:
• F = 0.5 * CSExtraDelay * GPMC_FCLK
• Case GpmcFCLKDivider = 1:
• F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are
even)
• F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise
• Case GpmcFCLKDivider = 2:
• F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 3)
• F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
• F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
(6) For single read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: E = (CSWrOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(7) B = ClkActivationTime * GPMC_FCLK
(8) For single read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: D = (WrCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 109
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