Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
6.2.4 Clock Duty Cycle Error
The maximum duty cycle error is the difference between the absolute value of the maximum high-level
pulse duration or the maximum low-level pulse duration and the typical pulse duration value:
• Maximum pulse duration = typical pulse duration + maximum duty cycle error
• Minimum pulse duration = typical pulse duration - maximum duty cycle error
6.3 Timing Parameters
The timing parameter symbols used in the timing requirement and switching characteristic tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other
related terminologies have been abbreviated as follows:
Table 6-1. Timing Parameters
LOWERCASE SUBSCRIPTS
Symbols Parameter
c Cycle time (period)
d Delay time
dis Disable time
en Enable time
h Hold time
su Setup time
START Start bit
t Transition time
v Valid time
w Pulse duration (width)
X Unknown, changing, or dont care level
H High
L Low
V Valid
IV Invalid
AE Active Edge
FE First Edge
LE Last Edge
Z High impedance
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 107
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