Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
(T
MIN
to T
MAX
, vdda_dac = 1.8 V, R
OUT1/2
= 1650 , R
LOAD
= 75 , unless otherwise noted)
Table 5-3. Video DAC Dynamic Electrical Specification
PARAMETER CONDITIONS/ASSUMPTIONS MIN TYP MAX UNIT
f
CLK
(1)
Output update rate Equal to input clock frequency 54 MHz
Clock jitter rms clock jitter required in order to assure 10- 40 ps
bit accuracy
Attenuation at 5.1 MHz Corner frequency for signal 0.1 0.5 1.5 dB
Attenuation at 54 MHz
(1)
Image frequency 25 30 33 dB
t
ST
Output settling time Time from the start of the output transition to 85 ns
output within 1 LSB of final value.
t
Rout
Output rise time Measured from 10% to 90% of full-scale 25 ns
transition
t
Fout
Output fall time Measured from 10% to 90% of full-scale 25 ns
transition
BW Signal bandwidth 6 MHz
Differential gain
(2)
1.5%
Differential phase
(2)
1 deg.
SFDR Within bandwidth f
CLK
= 54 MHz, f
OUT
= 1 MHz 45 dB
SNR Signal-to-noise ratio f
CLK
= 54 MHz, f
OUT
= 1 MHz 55
(3)
dB
1 kHz to 6 MHz bandwidth
PSRR Power supply rejection ratio Up to 6 MHz 20
(4)
dB
Crosstalk Between the two video 50 40 dB
channels
(1) For internal input clock information, For more information, see the Device Display Interface Subsystem Reference Guide [literature
number SPRUFV2].
(2) The differential gain and phase value is for dc coupling. Note that there is degradation for the ac coupling.
(3) The SNR value is for dc coupling. Note that there is a 6-dB degradation for ac coupling.
(4) The PSSR value is for dc coupling. Note that there is a 10-dB degradation for ac coupling.
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