Datasheet

Device
DSS
tv_vref
DIN1[9:0]
vssa_dacvdda_dac
Video DAC 1
TV DCT
Video DAC 2
TVOUT
BUFFER
DIN2[9:0]
TVOUT
BUFFER
TVOUT
BUFFER
tv_vfb1
tv_out1
CBG
tv_out2
tv_vfb2
V_ref
030-018
R
OUT1
R
OUT2
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
5 Video DAC Specifications
A dual-display interface equips the AM3517/05 processor. This display subsystem provides the necessary
control signals to interface the memory frame buffer directly to the external displays (TV-set). Two (one
per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to generate the
video analog signal. One of the video DACs also includes TV detection and power-down mode. Figure 5-1
illustrates the AM3517/05 DAC architecture.
Figure 5-1. Video DAC Architecture
The following paragraphs detail the 10-bit DAC interface pinout, static and dynamic specifications, and
noise requirements. The operating conditions and absolute maximum ratings are detailed in Table 5-2 and
Table 5-4.
100 Video DAC Specifications Copyright © 2009–2013, Texas Instruments Incorporated
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