Datasheet

P
R
Y
AA
AB
AC
AD
U
V
W
T
10 9 8
P
R
T
U
V
W
Y
AA
AB
AC
AD
CCDC_
PCLK
13
12 11
6 5
M
N
4
3
7
M
N
2 1
CCDC_
FIELD
CCDC_
VD
CCDC_
DATA0
CCDC_
DATA3
RMII_MDIO
_CLK
RMII_TXD0
RMII_TXEN
MMC1_
DAT1
MMC1_
DAT6
MMC2_CLK
MMC2_
DAT2
MMC2_
DAT6
VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS
VDDSHV
VSS
VSS
VSS
VSS
VSS
VSS VSS VSS VSS VSS VDDSHV
VDDSHV
VDDSHV
VDDSHV
VDDSHV
GPMC_
NCS5
GPMC_
NCS4
GPMC_
NCS3
GPMC_
NCS2
GPMC_
NCS7
GPMC_
NCS6
GPMC_CLK
UART3_CTS
_RCTX
UART3_RTS
_SD
UART3_RX
_IRRX
UART3_TX
_IRTX
GPMC_NADV
_ALE
GPMC_
NBE1
GPMC_
WAIT3
I2C2_SCL
SYS_NIRQ
SYS_
BOOT1
SYS_
BOOT4
SYS_
BOOT6
SYS_
BOOT7
SYS_
BOOT5
SYS_
BOOT2
SYS
_NRES
PWRON
SYS_
BOOT8
13
12 11
10 9 8
7
6 5
4
3
AE
2 1
AE
CCDC_
HD
VSS
CCDC_
WEN
CCDC_
DATA1
CCDC_
DATA4
RMII_MDIO
_DATA
RMII_TXD1
RMII_50MHZ
_CLK
MMC1_
DAT2
MMC1_
DAT7
MMC2_
CMD
MMC2_
DAT3
MMC2_
DAT7
MMC2_
DAT1
MMC2_
DAT5
MMC2_
DAT0
MMC2_
DAT4
VDDS_SRAM
_MPU
CAP_VDD_
SRAM_MPU
VDDSHV
VDDSHV
VDDSHV
MMC1_
DAT0
MMC1_
DAT5
MMC1_
CMD
MMC1_
DAT4
MMC1_CLK
MMC1_
DAT3
VDDSHV
VDDSHV
VDDSHV
VDDS
VDD_CORE VDD_CORE
VDD_CORE
VDD_CORE
VSS
VSS
VSS
VSS
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VSS VSS
VSS VSSVSS VSS
VSS VSS
CCDC_
DATA2
CCDC_
DATA7
CCDC_
DATA6
CCDC_
DATA5
VDDSHV
VDDSHV
VDDSHV
VDDSHV
RMII_RXER
RMII_CRS_
DV
RMII_RXD1
RMII_RXD0
VDDSHV
VDDSHV
VDDSHV
I2C3_SDA
I2C1_SDA
I2C3_SCL
I2C1_SCL
SYS_
BOOT3
SYS
_NRES
WARM
SYS_
BOOT0
I2C2_SDA
HECC1_
TXD
HECC1_
RXD
GPMC_
NWP
GPMC_
WAIT0
GPMC_
WAIT1
GPMC_
WAIT2
VDDS
GPMC_NBE0
_CLE
GPMC_
NWE
GPMC_
NOE
RESERVED
RESERVED
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Figure 2-2. ZCN Pin Map [Quadrant B]
10 Terminal Description Copyright © 2009–2013, Texas Instruments Incorporated
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