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AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

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SPRS717E –OCTOBER 2011–REVISED JANUARY 2013

• Changed Figure 4-12, OSC1 (ZCZ Package) Crystal Circuit Schematic .................................................. 107

• Changed Figure 4-14, OSC1 (ZCE Package) LVCMOS Circuit Schematic ............................................... 109

• Changed Figure 4-15, OSC1 (ZCZ Package) LVCMOS Circuit Schematic ............................................... 109

• Added Table 4-7, OSC1 LVCMOS Reference Clock Requirements ....................................................... 109

• Changed paragraph in Section 4.2.2.5, OSC1 Not Used .................................................................... 110

• Changed Figure 4-16, OSC1 (ZCE Package) Not Used Schematic ....................................................... 110

• Changed Figure 4-17, OSC1 (ZCZ Package) Not Used Schematic ....................................................... 110

• Added Note to Section 4.2.4, Output Clock Characteristics ................................................................. 111

• Moved Table 5-3, Ethernet MAC and Switch Timing Conditions to Section 5.4.1 ....................................... 114

• Added Section 5.4.1.1, Ethernet MAC/Switch MDIO Electrical Data and Timing ........................................ 114

• Changed Footnote (3) in Table 5-40, DQS[x] and DQ[x] Routing Specification .......................................... 153

• Changed Footnote (4) in Table 5-53, DQS[x] and DQ[x] Routing Specification .......................................... 165

• Changed Section 5.5.2.3 title to DDR3 and DDR3L Routing Guidelines .................................................. 166

• Added Note to Section 5.5.2.3 .................................................................................................. 166

• Changed footnote in Table 5-54, Switching Characteristics Over Recommended Operating Conditions for DDR3

Memory Interface ................................................................................................................. 166

• Changed Figure 5-46 and changed figure title to 16-Bit DDR3 Interface Using One 16-Bit DDR3 Device with V

Termination ........................................................................................................................ 167

• Added Figure 5-47, 16-Bit DDR3 Interface Using One 16-Bit DDR3 Device without V

Termination ................ 168

• Changed Figure 5-48, 16-Bit DDR3 Interface Using Two 8-Bit DDR3 Devices .......................................... 169

• Added paragraph to Section 5.5.2.3.3.9, DDR3 Signal Termination ....................................................... 175

• Changed Footnote (6) in Table 5-65, DQS[x] and DQ[x] Routing Specification .......................................... 184

• Deleted FAST MODE MIN values for Parameters 23-26 and deleted Footnote (1) in Table 5-68, Switching

Characteristics Over Recommended Operating Conditions for I2C Output Timings ..................................... 186

• Changed parameter 18 UNITs to ns in Table 5-70, Timing Requirements for LCD LIDD Mode ....................... 187

• Changed Parameter 1 OPP50 MIN value and Parameters 4, 6, 8, and 10 MAX values in Table 5-72, Switching

Characteristics Over Recommended Operating Conditions for LCD Raster Mode ...................................... 197

• Changed Figure 6-1, AM335x Device Nomenclature ........................................................................ 221

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