Datasheet

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AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com SPRS717E –OCTOBER 2011–REVISED JANUARY 2013
3.2 Recommended Operating Conditions
Device Operating Performance Points are defined in Table 3-2 through Table 3-7.
Table 3-2. VDD_CORE Operating Performance Points for ZCZ Package
with Device Revision Code "Blank"
(1)
VDD_CORE VDD_CORE
OPP DDR3,
DDR2
(2)
mDDR
(2)
L3 and L4
Device Rev. DDR3L
(2)
MIN NOM MAX
"Blank"
OPP100 1.056 V 1.100 V 1.144 V 303 MHz
(3)
266 MHz 200 MHz 200 MHz and
100 MHz
OPP50 0.912 V 0.950 V 0.988 V - 125 MHz 90 MHz 100 MHz and
50 MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) This parameter represents the maximum memory clock frequency. Since data is transferred on both edges of the clock, double-data rate
(DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
(3) The JEDEC JESD79-3F Standard defines the maximum clock period of 3.3 ns for all standard-speed bin DDR3 and DDR3L memory
devices. Therefore, all standard-speed bin DDR3 and DDR3L memory devices are required to operate at 303 MHz.
Table 3-3. VDD_MPU Operating Performance Points for ZCZ Package
with Device Revision Code "Blank"
(1)
VDD_MPU
VDD_MPU OPP
ARM (A8)
Device Rev. "Blank"
MIN NOM MAX
Turbo 1.210 V 1.260 V 1.326 V 720 MHz
OPP120 1.152 V 1.200 V 1.248 V 600 MHz
OPP100
(2)
1.056 V 1.100 V 1.144 V 500 MHz
OPP100
(3)
1.056 V 1.100 V 1.144 V 275 MHz
OPP50 0.912 V 0.950 V 0.988 V 275 MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) Applies to all orderable AM335_ZCZ_50 (500-MHz speed grade) or higher devices.
(3) Applies to all orderable AM335_ZCZ_27 (275-MHz speed grade) devices.
Table 3-4. VDD_CORE Operating Performance Points for ZCE Package
with Device Revision Code "Blank"
(1)
VDD_CORE VDD_MPU
(2)
OPP DDR3,
ARM (A8) DDR2
(3)
mDDR
(3)
L3 and L4
Device Rev. DDR3L
(3)
MIN NOM MAX
"Blank"
OPP100 1.056 V 1.100 V 1.144 V 500 MHz 303 MHz
(4)
266 MHz 200 MHz 200 MHz and
100 MHz
OPP100 1.056 V 1.100 V 1.144 V 275 MHz 303 MHz
(4)
266 MHz 200 MHz 200 MHz and
100 MHz
OPP50 0.912 V 0.950 V 0.988 V 275 MHz - 125 MHz 90 MHz 100 MHz and
50 MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) VDD_MPU is merged with VDD_CORE on the ZCE package.
(3) This parameter represents the maximum memory clock frequency. Since data is transferred on both edges of the clock, double-data rate
(DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
(4) The JEDEC JESD79-3F Standard defines the maximum clock period of 3.3 ns for all standard-speed bin DDR3 and DDR3L memory
devices. Therefore, all standard-speed bin DDR3 and DDR3L memory devices are required to operate at 303 MHz.
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