Datasheet

PRODUCTPREVIEW
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717E –OCTOBER 2011–REVISED JANUARY 2013 www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2012) to Revision E Page
• Changed ARM speeds features list item .......................................................................................... 1
• Added Features list item for DDR3L ............................................................................................... 1
• Changed Figure 1-1, AM335x Functional Block Diagram ...................................................................... 6
• Changed Notes 6, 7, and 8 in Section 2.2, Ball Characteristics ............................................................. 18
• Changed DDR_DQSn0 and DDR_DQSn1 Ball Reset State value in Table 2-7, Ball Characteristics (ZCE and
ZCZ Packages) ..................................................................................................................... 22
• Changed EXT_WAKEUP Ball Reset Rel. State value in Table 2-7, Ball Characteristics (ZCE and ZCZ
Packages) ........................................................................................................................... 23
• Added gpmc_a2 signal and footnote to LCD_HYSNC in Table 2-7, Ball Characteristics (ZCE and ZCZ
Packages) ........................................................................................................................... 34
• Added gpmc_a1 signal and footnote to LCD_VYSNC in Table 2-7, Ball Characteristics (ZCE and ZCZ
Packages) ........................................................................................................................... 35
• Added PWRONRSTn ZCE POWER/ZCZ POWER footnote in Table 2-7, Ball Characteristics (ZCE and ZCZ
Packages) ........................................................................................................................... 42
• Changed RTC_XTALIN Ball Reset State value, Ball Reset Rel. State value, and PULLUP/DOWN Type footnote
in Table 2-7, Ball Characteristics (ZCE and ZCZ Packages) ................................................................. 43
• Added Footnotes (7), (8), and (9) to Table 3-1, Absolute Maximum Ratings Over Junction Temperature Range .... 79
• Added paragraph to Section 3.1 .................................................................................................. 80
• Added Table 3-2, VDD_CORE Operating Performance Points for ZCZ Package with Device Revision Code
"Blank" ............................................................................................................................... 81
• Added Table 3-3, VDD_MPU Operating Performance Points for ZCZ Package with Device Revision Code
"Blank" ............................................................................................................................... 81
• Added Table 3-4, VDD_CORE Operating Performance Points for ZCE Package with Device Revision Code
"Blank" ............................................................................................................................... 81
• Added Table 3-5, VDD_CORE Operating Performance Points for ZCZ Package with Device Revision Code "A"
or Newer ............................................................................................................................. 82
• Added Table 3-6, VDD_MPU Operating Performance Points for ZCZ Package with Device Revision Code "A" or
Newer ................................................................................................................................ 82
• Added Table 3-7, VDD_CORE Operating Performance Points for ZCE Package with Device Revision Code "A"
or Newer ............................................................................................................................. 82
• Changed VDD_MPU Descriptions and MAX values in Table 3-8, Maximum Current Ratings at AM335x Power
Terminals ............................................................................................................................ 83
• Deleted VDD_MPU and VDD_CORE columns and Footnotes (1) and (2) from Table 3-9, Reliability Data ........... 84
• Updated MIN, NOM, and MAX values in Table 3-10, Recommended Operating Conditions ............................ 84
• Added Footnote (1) to Table 3-10, Recommended Operating Conditions .................................................. 84
• Added VDDS_DDR Parameter Description and Values for DDR IO domain DDR3L to Table 3-10 .................... 84
• Changed V
IH
and V
IL
Parameters and Values in Table 3-11, DC Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Temperature ...................................................................... 88
• Added PWRONRSTn section and Footnote (1) to Table 3-11, DC Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Temperature ...................................................................... 89
• Changed Footnote (4) in Table 3-13, Power-Supply Decoupling Capacitor Characteristics ............................. 92
• Changed figure and Footnote A in Figure 4-1, Preferred Power-Supply Sequencing with Dual-Voltage IOs
Configured as 3.3 V ................................................................................................................ 96
• Changed figure and Footnote A in Figure 4-2, Alternate Power-Supply Sequencing with Dual-Voltage IOs
Configured as 3.3 V ................................................................................................................ 97
• Changed figure and Footnote A in Figure 4-3, Power-Supply Sequencing with Dual-Voltage IOs Configured as
1.8 V .................................................................................................................................. 98
• Changed figure and Footnote A in Figure 4-4, Power-Supply Sequencing with Internal RTC LDO Disabled ......... 99
• Changed Figure 4-5, Power-Supply Sequencing with RTC Feature Disabled ............................................ 100
• Changed third and fourth paragraphs in Section 4.1.2, Power-Down Sequencing ...................................... 101
• Changed Figure 4-6, VDD_MPU_MON Connectivity ........................................................................ 101
• Changed Figure 4-8, OSC0 Crystal Circuit Schematic ...................................................................... 104
• Changed Figure 4-10, OSC0 LVCMOS Circuit Schematic .................................................................. 106
• Added Table 4-4, OSC0 LVCMOS Reference Clock Requirements ....................................................... 106
• Changed Figure 4-11, OSC1 (ZCE Package) Crystal Circuit Schematic .................................................. 107
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