Datasheet

PRODUCTPREVIEW
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com SPRS717E –OCTOBER 2011–REVISED JANUARY 2013
• Up to 48 MHz • Integrated DMA Engine to Pull Data from
the External Frame Buffer without
– Up to Three MMC, SD, and SDIO Ports
Burdening the Processor via Interrupts or
• 1-Bit, 4-Bit and 8-Bit MMC, SD, and SDIO
a Firmware Timer
Modes
• 512-Word Deep Internal FIFO
• MMCSD0 has dedicated Power Rail for
• Supported Display Types:
1.8-V or 3.3-V Operation
– Character Displays - Uses LCD
• Up to 48-MHz Data Transfer Rate
Interface Display Driver (LIDD)
• Supports Card Detect and Write Protect
Controller to Program these Displays
• Complies with MMC4.3 and SD and SDIO
– Passive Matrix LCD Displays - Uses
2.0 Specifications
LCD Raster Display Controller to
– Up to Three I2C Master and Slave Interfaces
Provide Timing and Data for Constant
• Standard Mode (up to 100 kHz)
Graphics Refresh to a Passive Display
• Fast Mode (up to 400 kHz)
– Active Matrix LCD Displays - Uses
– Up to Four Banks of General-Purpose IO
External Frame Buffer Space and the
(GPIO)
Internal DMA Engine to Drive
• 32 GPIOs per Bank (Multiplexed with
Streaming Data to the Panel
Other Functional Pins)
– 12-Bit Successive Approximation Register
• GPIOs Can be Used as Interrupt Inputs
(SAR) ADC
(Up to Two Interrupt Inputs per Bank)
• 200K Samples per Second
– Up to Three External DMA Event Inputs That
• Input Can be Selected from any of the
Can Also be Used as Interrupt Inputs
Eight Analog Inputs Multiplexed Through
– Eight 32-Bit General-Purpose Timers
an 8:1 analog Switch
• DMTIMER1 is a 1-ms Timer Used for
• Can be Configured to Operate as a 4-wire,
Operating System (OS) Ticks
5-wire, or 8-wire Resistive Touch Screen
Controller (TSC) Interface
• DMTIMER4 - DMTIMER7 are Pinned Out
– Up to Three 32-Bit Enhanced Capture
– One Watchdog Timer
Modules (eCAP)
– SGX530 3D Graphics Engine
• Configurable as Three Capture Inputs or
• Tile-Based Architecture Delivering Up to
Three Auxiliary PWM Outputs
20 Million Polygons per second
– Up to Three Enhanced High-Resolution PWM
• Universal Scalable Shader Engine is a
Modules (eHRPWM)
Multi-Threaded Engine Incorporating
• Dedicated 16-Bit Time-Base Counter with
Pixel and Vertex Shader Functionality
Time and Frequency Controls
• Advanced Shader Feature Set in Excess
• Configurable as Six Single-Ended, Six
of Microsoft VS3.0, PS3.0 and OGL2.0
Dual-Edge Symmetric, or Three Dual-
• Industry Standard API Support of
Edge Asymmetric Outputs
Direct3D Mobile, OGL-ES 1.1 and 2.0,
– Up to Three 32-Bit Enhanced Quadrature
OpenVG 1.0, and OpenMax
Encoder Pulse (eQEP) Modules
• Fine-Grained Task Switching, Load
• Device Identification
Balancing and Power Management
– Contains Electrical fuse Farm (FuseFarm) of
• Advanced Geometry DMA Driven
Which Some Bits are Factory Programmable
Operation for Minimum CPU Interaction
• Production ID
• Programmable High-Quality Image Anti-
Aliasing
• Device Part Number (Unique JTAG ID)
• Fully Virtualized Memory Addressing for
• Device Revision (readable by Host ARM)
OS Operation in a Unified Memory
• Debug Interface Support
Architecture
– JTAG and cJTAG for ARM (Cortex-A8 and
– LCD Controller
PRCM), PRU-ICSS Debug
• Up to 24-Bits Data Output; 8-Bits per
– Embedded Trace Module (ETM) and
Pixel (RGB)
Embedded Trace Buffer (ETB)
• Resolution Up to 2048x2048 (With
– Supports Device Boundary Scan
Maximum 126-MHz Pixel Clock)
– Supports IEEE 1500
• Integrated LCD Interface Display Driver
• DMA
(LIDD) Controller
– On-Chip Enhanced DMA Controller (EDMA)
• Integrated Raster Controller
has Three Third-Party Transfer Controllers
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