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10
MMC[x]_CLK (Output)
MMC[x]_CMD (Output)
MMC[x]_DAT[7:0] (Outputs)
11
RMII[x]_REFCLK
(Input)
5
7
6
8
9
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com SPRS717E –OCTOBER 2011–REVISED JANUARY 2013
Table 5-84. Switching Characteristics for MMC[x]_CLK
(see Figure 5-91)
STANDARD MODE HIGH-SPEED MODE
NO. PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
f
op(CLK)
Operating frequency, MMC_CLK 24 48 MHz
t
cop(CLK)
Operating period: MMC_CLK 41.7 20.8 ns
5
f
id(CLK)
Identification mode frequency, MMC_CLK 400 400 kHz
t
cid(CLK)
Identification mode period: MMC_CLK 2500 2500 ns
(0.5*P) - (0.5*P) -
6 t
w(CLKL)
Pulse duration, MMC_CLK low ns
t
f(CLK)
(1)
t
f(CLK)
(1)
(0.5*P) - (0.5*P) -
7 t
w(CLKH)
Pulse duration, MMC_CLK high ns
t
r(CLK)
(1)
t
r(CLK)
(1)
8 t
r(CLK)
Rise time, All Signals (10% to 90%) 2.2 2.2 ns
9 t
f(CLK)
Fall time, All Signals (10% to 90%) 2.2 2.2 ns
(1) P = MMC_CLK period.
Figure 5-91. MMC[x]_CLK Timing
Table 5-85. Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—Standard Mode
(see Figure 5-92)
NO. PARAMETER MIN TYP MAX UNIT
Delay time, MMC_CLK falling clock edge to MMC_CMD
10 t
d(CLKL-CMD)
-4 14 ns
transition
Delay time, MMC_CLK falling clock edge to MMC_DATx
11 t
d(CLKL-DAT)
-4 14 ns
transition
Figure 5-92. MMC[x]_CMD and MMC[x]_DAT[7:0] Output Timing—Standard Mode
Copyright © 2011–2013, Texas Instruments Incorporated Peripheral Information and Timings 215
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