Datasheet

PRODUCTPREVIEW
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com SPRS717E –OCTOBER 2011–REVISED JANUARY 2013
5.9.1.2 McSPI—Master Mode
Table 5-79. McSPI Timing Conditions—Master Mode
LOW LOAD HIGH LOAD
TIMING CONDITION PARAMETER UNIT
MIN MAX MIN MAX
Input Conditions
t
r
Input signal rise time 8 16 ns
t
f
Input signal fall time 8 16 ns
Output Condition
C
load
Output load capacitance 5 25 pF
Table 5-80. Timing Requirements for McSPI Input Timings—Master Mode
(see Figure 5-88)
LOW LOAD HIGH LOAD
NO. UNIT
MIN MAX MIN MAX
Setup time, SPI_D[x] (SOMI) valid before SPI_CLK active
4 t
su(SOMI-SPICLKH)
2.29 3.02 ns
edge
(1)
Hold time, SPI_D[x] (SOMI) valid after SPI_CLK active
5 t
h(SPICLKH-SOMI)
2.67 2.76 ns
edge
(1)
(1) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
Table 5-81. Switching Characteristics Over Recommended Operating Conditions for McSPI Output
Timings—Master Mode
(see Figure 5-89)
LOW LOAD HIGH LOAD
NO. PARAMETER UNIT
MIN MAX MIN MAX
1 t
c(SPICLK)
Cycle time, SPI_CLK 20.8 20.8 ns
2 t
w(SPICLKL)
Typical Pulse duration, SPI_CLK low 0.5P
(1)
0.5P
(1)
0.5P
(1)
TBD ns
t
w(SPICLKH)
Typical Pulse duration, SPI_CLK high 0.5P
(1)
0.5P
(1)
0.5P
(1)
TBD ns
3 t
r(SPICLK)
Rising time, SPI_CLK 3.82 10.685 ns
t
f(SPICLK)
Falling time, SPI_CLK 3.44 10.685 ns
Delay time, SPI_CLK active edge to SPI_D[x] (SIMO)
6 t
d(SPICLK-SIMO)
-3.57 3.57 -4.62 4.62 ns
transition
(2)
Delay time, SPI_CS active edge to SPI_D[x] (SIMO)
7 t
d(CS-SIMO)
3.57 4.62 ns
transition
(2)
Mode 1 and 3
(3)
A-4.2
(4)
A-2.54
(4)
ns
Delay time, SPI_CS active to SPI_CLK
8 t
d(CS-SPICLK)
first edge
Mode 0 and 2
(3)
B-4.2
(5)
B-2.54
(5)
ns
Mode 1 and 3
(3)
B-4.2
(5)
B-2.54
(5)
ns
Delay time, SPI_CLK last edge to
9 t
d(SPICLK-CS)
SPI_CS inactive
Mode 0 and 2
(3)
A-4.2
(4)
A-2.54
(4)
ns
(1) P = SPI_CLK period.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
(3) The polarity of SPIx_CLK and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable:
– SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 1 (Modes 1 and 3).
– SPIx_CLK(1) phase programmable with the bit PHA of MCSPI_CH(i)CONF register: PHA = 0 (Modes 0 and 2).
(4) Case P = 20.8 ns, A = (TCS+1)*TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
Case P > 20.8 ns, A = (TCS+0.5)*Fratio*TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
Note: P = SPI_CLK clock period.
(5) B = (TCS+0.5)*TSPICLKREF*Fratio (TCS is a bit field of MCSPI_CH(i)CONF register, Fratio: Even≥2).
Copyright © 2011–2013, Texas Instruments Incorporated Peripheral Information and Timings 211
Submit Documentation Feedback
Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352