Datasheet

PRODUCTPREVIEW
8
7
4
4
3
2
2
1
A0 A1 B0 B1A30 A31 B30 B31 C0 C1 C2 C3 C31
MCA[x]_ACLKR/X (Falling Edge Polarity)
MCA[x]_AHCLKR/X (Rising Edge Polarity)
MCA[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCA[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCA[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 2 Bit Delay)
MCA[x]_AXR[x] (Data In/Receive)
6
5
MCA[x]_ACLKR/X (CLKRP = CLKXP = 0)
(A)
MCA[x]_ACLKR/X (CLKRP = CLKXP = 1)
(B)
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com SPRS717E –OCTOBER 2011–REVISED JANUARY 2013
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 5-84. McASP Input Timing
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