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SPRS717E –OCTOBER 2011–REVISED JANUARY 2013 www.ti.com
5.8.2 McASP Electrical Data and Timing
Table 5-73. McASP Timing Conditions
TIMING CONDITION PARAMETER MIN TYP MAX UNIT
Input Conditions
t
R
Input signal rise time 1
(1)
4
(1)
ns
t
F
Input signal fall time 1
(1)
4
(1)
ns
Output Condition
C
LOAD
Output load capacitance 15 30 pF
(1) Except when specified otherwise.
Table 5-74. Timing Requirements for McASP
(1)
(see Figure 5-84)
NO. MIN MAX UNIT
1 t
c(AHCLKRX)
Cycle time, MCA[x]_AHCLKR and MCA[x]_AHCLKX 20 ns
0.5P -
2 t
w(AHCLKRX)
Pulse duration, MCA[x]_AHCLKR and MCA[x]_AHCLKX high or low ns
2.5
(2)
3 t
c(ACLKRX)
Cycle time, MCA[x]_ACLKR and MCA[x]_ACLKX 20 ns
0.5R -
4 t
w(ACLKRX)
Pulse duration, MCA[x]_ACLKR and MCA[x]_ACLKX high or low ns
2.5
(3)
ACLKR and
11.5
ACLKX int
t
su(AFSRX-
Setup time, MCA[x]_AFSR and MCA[x]_AFSX input valid before ACLKR and
5 4 ns
ACLKRX)
MCA[X]_ACLKR and MCA[X]_ACLKX ACLKX ext in
ACLKR and
4
ACLKX ext out
ACLKR and
-1
ACLKX int
t
h(ACLKRX-
Hold time, MCA[x]_AFSR and MCA[x]_AFSX input valid after ACLKR and
6 2 ns
AFSRX)
MCA[X]_ACLKR and MCA[X]_ACLKX ACLKX ext in
ACLKR and
2
ACLKX ext out
ACLKR and
11.5
ACLKX int
Setup time, MCA[x]_AXR input valid before MCA[X]_ACLKR ACLKR and
7 t
su(AXR-ACLKRX)
4 ns
and MCA[X]_ACLKX ACLKX ext in
ACLKR and
4
ACLKX ext out
ACLKR and
-1
ACLKX int
Hold time, MCA[x]_AXR input valid after MCA[X]_ACLKR and ACLKR and
8 t
h(ACLKRX-AXR)
2 ns
MCA[X]_ACLKX ACLKX ext in
ACLKR and
2
ACLKX ext out
(1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
(2) P = MCA[X]_AHCLKR and MCA[X]_AHCLKX period in nano seconds (ns).
(3) R = MCA[X]_ACLKR and MCA[X]_ACLKX period in ns.
204 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated
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