Datasheet

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AM3359, AM3358, AM3357
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www.ti.com SPRS717E –OCTOBER 2011–REVISED JANUARY 2013
5.7.2 LCD Raster Mode
Table 5-72. Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode
(see Figure 5-80 through Figure 5-83)
OPP50 OPP100
NO. PARAMETER UNIT
MIN MAX MIN MAX
1 t
c(LCD_PCLK)
Cycle time, pixel clock 15.8 7.9 ns
2 t
w(LCD_PCLKH)
Pulse duration, pixel clock high 0.45t
c
0.55t
c
0.45t
c
0.55t
c
ns
3 t
w(LCD_PCLKL)
Pulse duration, pixel clock low 0.45t
c
0.55t
c
0.45t
c
0.55t
c
ns
Delay time, LCD_PCLK to LCD_DATA[23:0] valid
4 t
d(LCD_PCLK-LCD_DATAV)
1.2 1 ns
(write)
Delay time, LCD_PCLK to LCD_DATA[23:0] invalid
5 t
d(LCD_PCLK-LCD_DATAI)
-1.5 -1 ns
(write)
6 t
d(LCD_PCLK-LCD_AC_BIAS_EN)
Delay time, LCD_PCLK to LCD_AC_BIAS_EN -1.5 1.2 -1 1 ns
7 t
t(LCD_AC_BIAS_EN)
Transition time, LCD_AC_BIAS_EN 0.5 2.4 0.5 2.4 ns
8 t
d(LCD_PCLK-LCD_VSYNC)
Delay time, LCD_PCLK to LCD_VSYNC -1.5 1.2 -1 1 ns
9 t
t(LCD_VSYNC)
Transition time, LCD_VSYNC 0.5 2.4 0.5 2.4 ns
10 t
d(LCD_PCLK-LCD_HSYNC)
Delay time, LCD_PCLK to LCD_HSYNC -1.5 1.2 -1 1 ns
11 t
t(LCD_HSYNC)
Transition time, LCD_HSYNC 0.5 2.4 0.5 2.4 ns
12 t
t(LCD_PCLK)
Transition time, LCD_PCLK 0.5 2.4 0.5 2.4 ns
13 t
t(LCD_DATA)
Transition time, LCD_DATA 0.5 2.4 0.5 2.4 ns
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:
• Vertical front porch (VFP)
• Vertical sync pulse width (VSW)
• Vertical back porch (VBP)
• Lines per panel (LPP_B10 + LPP)
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
• Horizontal front porch (HFP)
• Horizontal sync pulse width (HSW)
• Horizontal back porch (HBP)
• Pixels per panel (PPLMSB + PPLLSB)
LCD_AC_BIAS_EN timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:
• AC bias frequency (ACB)
The display format produced in raster mode is shown in Figure 5-79. An entire frame is delivered one line
at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of IO signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of IO signal LCD_HSYNC.
Copyright © 2011–2013, Texas Instruments Incorporated Peripheral Information and Timings 197
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