Datasheet

PRODUCTPREVIEW
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com SPRS717E –OCTOBER 2011–REVISED JANUARY 2013
5.7 LCD Controller (LCDC)
The LCD controller consists of two independent controllers, the raster controller and the LCD interface
display driver (LIDD) controller. Each controller operates independently from the other and only one of
them is active at any given time.
• The raster controller handles the synchronous LCD interface. It provides timing and data for constant
graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display
types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale and
serializer. Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous
memory block in the system. A built-in DMA engine supplies the graphics data to the raster engine
which, in turn, outputs to the external LCD device.
• The LIDD controller supports the asynchronous LCD interface. It provides full-timing programmability of
control signals (CS, WE, OE, ALE) and output data.
The maximum resolution for the LCD controller is 2048 x 2048 pixels. The maximum frame rate is
determined by the image size in combination with the pixel clock rate.
Table 5-69. LCD Controller Timing Conditions
TIMING CONDITION PARAMETER MIN TYP MAX UNIT
Output Condition
LIDD mode 5 60 pF
C
LOAD
Output load capacitance
Raster mode 3 30 pF
5.7.1 LCD Interface Display Driver (LIDD Mode)
Table 5-70. Timing Requirements for LCD LIDD Mode
(see Figure 5-70 through Figure 5-78)
OPP100
NO. PARAMETER UNIT
MIN MAX
Setup time, LCD_DATA[15:0] valid before
16 t
su(LCD_DATA-LCD_MEMORY_CLK)
18 ns
LCD_MEMORY_CLK high
Hold time, LCD_DATA[15:0] valid after
17 t
h(LCD_MEMORY_CLK-LCD_DATA)
0 ns
LCD_MEMORY_CLK high
18 t
t(LCD_DATA)
Transition time, LCD_DATA[15:0] 1 3 ns
Table 5-71. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode
(see Figure 5-70 through Figure 5-78)
OPP100
NO. PARAMETER UNIT
MIN MAX
1 t
c(LCD_MEMORY_CLK)
Cycle time, LCD_MEMORY_CLK 23.7 ns
2 t
w(LCD_MEMORY_CLKH)
Pulse duration, LCD_MEMORY_CLK high 0.45t
c
0.55t
c
ns
3 t
w(LCD_MEMORY_CLKL)
Pulse duration, LCD_MEMORY_CLK low 0.45t
c
0.55t
c
ns
Delay time, LCD_MEMORY_CLK high to
4 t
d(LCD_MEMORY_CLK-LCD_DATAV)
7 ns
LCD_DATA[15:0] valid (write)
Delay time, LCD_MEMORY_CLK high to
5 t
d(LCD_MEMORY_CLK-LCD_DATAI)
0 ns
LCD_DATA[15:0] invalid (write)
Delay time, LCD_MEMORY_CLK high to
6 t
d(LCD_MEMORY_CLK-LCD_AC_BIAS_EN)
0 6.8 ns
LCD_AC_BIAS_EN
7 t
t(LCD_AC_BIAS_EN)
Transition time, LCD_AC_BIAS_EN 1 10 ns
Delay time, LCD_MEMORY_CLK high to
8 t
d(LCD_MEMORY_CLK-LCD_VSYNC)
0 7 ns
LCD_VSYNC
9 t
t(LCD_VSYNC)
Transition time, LCD_VSYNC 1 10 ns
Delay time, LCD_MEMORY_CLK high to
10 t
d(LCD_MEMORY_CLK-LCD_HYSNC)
0 7 ns
LCD_HSYNC
Copyright © 2011–2013, Texas Instruments Incorporated Peripheral Information and Timings 187
Submit Documentation Feedback
Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352