Datasheet

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AS
=
Rtt
A1
A2
AT
Vtt
AS+
AS-
=
Rcp
Rcp
Cac
VDDS_DDR
0.1 µF
A1
A2
AT
A2
AT
A1
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717E –OCTOBER 2011–REVISED JANUARY 2013 www.ti.com
5.5.2.3.4.2.2 CK and ADDR_CTRL Routing, One DDR3 Device
Figure 5-59 shows the CK routing for one DDR3 device. Figure 5-60 shows the corresponding
ADDR_CTRL routing.
Figure 5-59. CK Routing for One DDR3 Device
Figure 5-60. ADDR_CTRL Routing for One DDR3 Device
5.5.2.3.5 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point to point, so its
definition is simple.
5.5.2.3.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
DQS[x] lines are point-to-point differential, and DQ[x] lines are point-to-point singled ended. Figure 5-61
and Figure 5-62 show these topologies.
180 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated
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