Datasheet

PRODUCTPREVIEW
A1 A2
AM335x
Address and Control
Output Buffer
DDR3 Address and Control Input Buffers
AT
Vtt
Address and Control
Terminator
Rtt
AS
A1 A2
AM335x
Differential Clock
Output Buffer
DDR3 Differential CK Input Buffer
Routed as Differential Pair
AT
Rcp
Clock Parallel
Terminator
A1 A2
AT
AS-
AS+
Rcp
Cac
VDDS_DDR
0.1 µF
+
–
+
–
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com SPRS717E –OCTOBER 2011–REVISED JANUARY 2013
5.5.2.3.4.2 One DDR3 Device
A single DDR3 device is supported on the DDR3 interface consisting of one x16 DDR3 device arranged
as one 16-bit bank.
5.5.2.3.4.2.1 CK and ADDR_CTRL Topologies, One DDR3 Device
Figure 5-57 shows the topology of the CK net classes and Figure 5-58 shows the topology for the
corresponding ADDR_CTRL net classes.
Figure 5-57. CK Topology for One DDR3 Device
Figure 5-58. ADDR_CTRL Topology for One DDR3 Device
Copyright © 2011–2013, Texas Instruments Incorporated Peripheral Information and Timings 179
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Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352