Datasheet

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SPRS717E –OCTOBER 2011–REVISED JANUARY 2013 www.ti.com
5.5.2.1.2.2 Compatible JEDEC LPDDR Devices
Table 5-30 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface.
Generally, the LPDDR interface is compatible with x16 LPDDR400 speed grade LPDDR devices.
Table 5-30. Compatible JEDEC LPDDR Devices (Per Interface)
(1)
NO. PARAMETER MIN MAX UNIT
1 JEDEC LPDDR device speed grade LPDDR400
2 JEDEC LPDDR device bit width x16 x16 Bits
3 JEDEC LPDDR device count 1 Devices
4 JEDEC LPDDR device terminal count 60 Terminals
(1) If the LPDDR interface is operated with a clock frequency less than 200 MHz, lower-speed grade LPDDR devices may be used if the
minimum clock period specified for the LPDDR device is less than or equal to the minimum clock period selected for the AM335x
LPDDR interface.
5.5.2.1.2.3 PCB Stackup
The minimum stackup required for routing the AM335x device is a four-layer stackup as shown in Table 5-
31. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal
integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
Table 5-31. Minimum PCB Stackup(1)
LAYER TYPE DESCRIPTION
1 Signal Top signal routing
2 Plane Ground
3 Plane Split Power Plane
4 Signal Bottom signal routing
(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these
signals on layer 1 which requires some to be routed on layer 4. When this is done, the signal routes on layer 4 should not cross splits in
the power plane.
146 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated
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