Datasheet

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www.ti.com SPRS717E –OCTOBER 2011–REVISED JANUARY 2013
Table 5-28. GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
OPP100 OPP50
NO. PARAMETER UNIT
MIN MAX MIN MAX
t
R(d)
Rise time, output data gpmc_ad[15:0] 2 2 ns
t
F(d)
Fall time, output data gpmc_ad[15:0] 2 2 ns
GNF0 t
w(wenV)
Pulse duration, output write enable gpmc_wen A
(1)
A
(1)
ns
valid
GNF1 t
d(csnV-wenV)
Delay time, output chip select gpmc_csn[x]
(13)
B
(2)
– 0.2 B
(2)
+ 2.0 B
(2)
– 0.2 B
(2)
+ 2.0 ns
valid to output write enable gpmc_wen valid
GNF2 t
w(cleH-wenV)
Delay time, output lower-byte enable and C
(3)
– 0.2 C
(3)
+ 2.0 C
(3)
– 0.2 C
(3)
+ 2.0 ns
command latch enable gpmc_be0n_cle high to
output write enable gpmc_wen valid
GNF3 t
w(wenV-dV)
Delay time, output data gpmc_ad[15:0] valid to D
(4)
– 0.2 D
(4)
+ 2.0 D
(4)
– 0.2 D
(4)
+ 2.0 ns
output write enable gpmc_wen valid
GNF4 t
w(wenIV-dIV)
Delay time, output write enable gpmc_wen E
(5)
– 0.2 E
(5)
+ 2.0 E
(5)
– 0.2 E
(5)
+ 2.0 ns
invalid to output data gpmc_ad[15:0] invalid
GNF5 t
w(wenIV-cleIV)
Delay time, output write enable gpmc_wen F
(6)
– 0.2 F
(6)
+ 2.0 F
(6)
– 0.2 F
(6)
+ 2.0 ns
invalid to output lower-byte enable and command
latch enable gpmc_be0n_cle invalid
GNF6 t
w(wenIV-csnIV)
Delay time, output write enable gpmc_wen G
(7)
– 0.2 G
(7)
+ 2.0 G
(7)
– 0.2 G
(7)
+ 2.0 ns
invalid to output chip select gpmc_csn[x]
(13)
invalid
GNF7 t
w(aleH-wenV)
Delay time, output address valid and address C
(3)
– 0.2 C
(3)
+ 2.0 C
(3)
– 0.2 C
(3)
+ 2.0 ns
latch enable gpmc_advn_ale high to output write
enable gpmc_wen valid
GNF8 t
w(wenIV-aleIV)
Delay time, output write enable gpmc_wen F
(6)
– 0.2 F
(6)
+ 2.0 F
(6)
– 0.2 F
(6)
+ 2.0 ns
invalid to output address valid and address latch
enable gpmc_advn_ale invalid
GNF9 t
c(wen)
Cycle time, write H
(8)
H
(8)
ns
GNF10 t
d(csnV-oenV)
Delay time, output chip select gpmc_csn[x]
(13)
I
(9)
– 0.2 I
(9)
+ 2.0 I
(9)
– 0.2 I
(9)
+ 2.0 ns
valid to output enable gpmc_oen valid
GNF13 t
w(oenV)
Pulse duration, output enable gpmc_oen valid K
(10)
K
(10)
ns
GNF14 t
c(oen)
Cycle time, read L
(11)
L
(11)
ns
GNF15 t
w(oenIV-csnIV)
Delay time, output enable gpmc_oen invalid to M
(12)
– 0.2 M
(12)
+ 2.0 M
(12)
– 0.2 M
(12)
+ 2.0 ns
output chip select gpmc_csn[x]
(13)
invalid
(1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(14)
(2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(14)
(3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK
(14)
(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay) * GPMC_FCLK
(14)
(5) E = ((WrCycleTime – WEOffTime) * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay) * GPMC_FCLK
(14)
(6) F = ((ADVWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay)) * GPMC_FCLK
(14)
(7) G = ((CSWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay)) * GPMC_FCLK
(14)
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(14)
(9) I = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(14)
(10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK
(14)
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(14)
(12) M = ((CSRdOffTime – OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay)) * GPMC_FCLK
(14)
(13) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4 or 5.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
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