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SPRS717E –OCTOBER 2011–REVISED JANUARY 2013 www.ti.com
5.5.1.3 GPMC and NAND Flash—Asynchronous Mode
Table 5-26 and Table 5-27 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-27 through Figure 5-30).
Table 5-25. GPMC and NAND Flash Timing Conditions—Asynchronous Mode
TIMING CONDITION PARAMETER MIN TYP MAX UNIT
Input Conditions
t
R
Input signal rise time 1 5 ns
t
F
Input signal fall time 1 5 ns
Output Condition
C
LOAD
Output load capacitance 3 30 pF
Table 5-26. GPMC and NAND Flash Internal Timing Parameters—Asynchronous Mode
(1)(2)
OPP100 OPP50
NO. UNIT
MIN MAX MIN MAX
GNFI1 Delay time, output data gpmc_ad[15:0] generation from internal 6.5 6.5 ns
functional clock GPMC_FCLK
(3)
GNFI2 Delay time, input data gpmc_ad[15:0] capture from internal functional 4.0 4.0 ns
clock GPMC_FCLK
(3)
GNFI3 Delay time, output chip select gpmc_csn[x] generation from internal 6.5 6.5 ns
functional clock GPMC_FCLK
(3)
GNFI4 Delay time, output address valid and address latch enable 6.5 6.5 ns
gpmc_advn_ale generation from internal functional clock
GPMC_FCLK
(3)
GNFI5 Delay time, output lower-byte enable and command latch enable 6.5 6.5 ns
gpmc_be0n_cle generation from internal functional clock
GPMC_FCLK
(3)
GNFI6 Delay time, output enable gpmc_oen generation from internal functional 6.5 6.5 ns
clock GPMC_FCLK
(3)
GNFI7 Delay time, output write enable gpmc_wen generation from internal 6.5 6.5 ns
functional clock GPMC_FCLK
(3)
GNFI8 Skew, functional clock GPMC_FCLK
(3)
100 100 ps
(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock.
Table 5-27. GPMC and NAND Flash Timing Requirements—Asynchronous Mode
OPP100 OPP50
NO. UNIT
MIN MAX MIN MAX
GNF12
(1)
t
acc(d)
Access time, input data gpmc_ad[15:0] J
(2)
J
(2)
ns
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
(3)
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
140 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated
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