Datasheet

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SPRS717E –OCTOBER 2011–REVISED JANUARY 2013 www.ti.com
Table 5-23. GPMC and NOR Flash Timing Requirements—Asynchronous Mode
NO. OPP100 OPP50 UNIT
MIN MAX MIN MAX
FA5
(1)
t
acc(d)
Data access time H
(5)
H
(5)
ns
FA20
(2)
t
acc1-pgmode(d)
Page mode successive data access time P
(4)
P
(4)
ns
FA21
(3)
t
acc2-pgmode(d)
Page mode first data access time H
(5)
H
(5)
ns
(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock
edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock
edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
(4) P = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
(6)
(5) H = AccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
(6)
(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
Table 5-24. GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
OPP100 OPP50
NO. PARAMETER UNIT
MIN MAX MIN MAX
t
R(d)
Rise time, output data gpmc_ad[15:0] 2 2 ns
t
F(d)
Fall time, output data gpmc_ad[15:0] 2 2 ns
FA0 t
w(be[x]nV)
Pulse duration, output lower-byte Read N
(12)
N
(12)
ns
enable and command latch enable
Write N
(12)
N
(12)
gpmc_be0n_cle, output upper-byte
enable gpmc_be1n valid time
FA1 t
w(csnV)
Pulse duration, output chip select Read A
(1)
A
(1)
ns
gpmc_csn[x]
(13)
low
Write A
(1)
A
(1)
FA3 t
d(csnV-advnIV)
Delay time, output chip select Read B
(2)
– 0.2 B
(2)
+ 2.0 B
(2)
– 0.2 B
(2)
+ 2.0 ns
gpmc_csn[x]
(13)
valid to output
Write B
(2)
– 0.2 B
(2)
+ 2.0 B
(2)
– 0.2 B
(2)
+ 2.0
address valid and address latch
enable gpmc_advn_ale invalid
FA4 t
d(csnV-oenIV)
Delay time, output chip select gpmc_csn[x]
(13)
C
(3)
– 0.2 C
(3)
+ 2.0 C
(3)
– 0.2 C
(3)
+ 2.0 ns
valid to output enable gpmc_oen invalid (Single
read)
FA9 t
d(aV-csnV)
Delay time, output address gpmc_a[27:1] valid J
(9)
– 0.2 J
(9)
+ 2.0 J
(9)
– 0.2 J
(9)
+ 2.0 ns
to output chip select gpmc_csn[x]
(13)
valid
FA10 t
d(be[x]nV-csnV)
Delay time, output lower-byte enable and J
(9)
– 0.2 J
(9)
+ 2.0 J
(9)
– 0.2 J
(9)
+ 2.0 ns
command latch enable gpmc_be0n_cle, output
upper-byte enable gpmc_be1n valid to output
chip select gpmc_csn[x]
(13)
valid
FA12 t
d(csnV-advnV)
Delay time, output chip select gpmc_csn[x]
(13)
K
(10)
– 0.2 K
(10)
+ 2.0 K
(10)
– 0.2 K
(10)
+ 2.0 ns
valid to output address valid and address latch
enable gpmc_advn_ale valid
FA13 t
d(csnV-oenV)
Delay time, output chip select gpmc_csn[x]
(13)
L
(11)
– 0.2 L
(11)
+ 2.0 L
(11)
– 0.2 L
(11)
+ 2.0 ns
valid to output enable gpmc_oen valid
FA16 t
w(aIV)
Pulse durationm output address gpmc_a[26:1] G
(7)
G
(7)
ns
invalid between 2 successive read and write
accesses
FA18 t
d(csnV-oenIV)
Delay time, output chip select gpmc_csn[x]
(13)
I
(8)
– 0.2 I
(8)
+ 2.0 I
(8)
– 0.2 I
(8)
+ 2.0 ns
valid to output enable gpmc_oen invalid (Burst
read)
FA20 t
w(aV)
Pulse duration, output address gpmc_a[27:1] D
(4)
D
(4)
ns
valid – 2nd, 3rd, and 4th accesses
FA25 t
d(csnV-wenV)
Delay time, output chip select gpmc_csn[x]
(13)
E
(5)
– 0.2 E
(5)
+ 2.0 E
(5)
– 0.2 E
(5)
+ 2.0 ns
valid to output write enable gpmc_wen valid
132 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated
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