Datasheet

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AM3359, AM3358, AM3357
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www.ti.com SPRS717E –OCTOBER 2011–REVISED JANUARY 2013
Table 5-20. GPMC and NOR Flash Switching Characteristics—Synchronous Mode
(2)
NO. PARAMETER OPP100 UNIT
MIN MAX
F0 1 / t
c(clk)
Frequency
(15)
, output clock gpmc_clk 100 MHz
F1 t
w(clkH)
Typical pulse duration, output clock gpmc_clk high 0.5P
(12)
0.5P
(12)
ns
F1 t
w(clkL)
Typical pulse duration, output clock gpmc_clk low 0.5P
(12)
0.5P
(12)
ns
t
dc(clk)
Duty cycle error, output clock gpmc_clk –500 500 ps
t
J(clk)
Jitter standard deviation
(16)
, output clock gpmc_clk 33.33 ps
t
R(clk)
Rise time, output clock gpmc_clk 2 ns
t
F(clk)
Fall time, output clock gpmc_clk 2 ns
t
R(do)
Rise time, output data gpmc_ad[15:0] 2 ns
t
F(do)
Fall time, output data gpmc_ad[15:0] 2 ns
F2 t
d(clkH-csnV)
Delay time, output clock gpmc_clk rising edge to output chip F
(6)
– 2.2 F
(6)
+ 4.5 ns
select gpmc_csn[x]
(11)
transition
F3 t
d(clkH-csnIV)
Delay time, output clock gpmc_clk rising edge to output chip E
(5)
– 2.2 E
(5)
+ 4.5 ns
select gpmc_csn[x]
(11)
invalid
F4 t
d(aV-clk)
Delay time, output address gpmc_a[27:1] valid to output clock B
(2)
– 4.5 B
(2)
+ 2.3 ns
gpmc_clk first edge
F5 t
d(clkH-aIV)
Delay time, output clock gpmc_clk rising edge to output address –2.3 4.5 ns
gpmc_a[27:1] invalid
F6 t
d(be[x]nV-clk)
Delay time, output lower byte enable and command latch B
(2)
– 1.9 B
(2)
+ 2.3 ns
enable gpmc_be0n_cle, output upper byte enable gpmc_be1n
valid to output clock gpmc_clk first edge
F7 t
d(clkH-be[x]nIV)
Delay time, output clock gpmc_clk rising edge to output lower D
(4)
– 2.3 D
(4)
+ 1.9 ns
byte enable and command latch enable gpmc_be0n_cle, output
upper byte enable gpmc_be1n invalid
F8 t
d(clkH-advn)
Delay time, output clock gpmc_clk rising edge to output address G
(7)
+ 2.3 G
(7)
+ 4.5 ns
valid and address latch enable gpmc_advn_ale transition
F9 t
d(clkH-advnIV)
Delay time, output clock gpmc_clk rising edge to output address D
(4)
– 2.3 D
(4)
+ 3.5 ns
valid and address latch enable gpmc_advn_ale invalid
F10 t
d(clkH-oen)
Delay time, output clock gpmc_clk rising edge to output enable H
(8)
– 2.3 H
(8)
+ 3.5 ns
gpmc_oen transition
F11 t
d(clkH-oenIV)
Delay time, output clock gpmc_clk rising edge to output enable E
(5)
– 2.3 E
(5)
+ 3.5 ns
gpmc_oen invalid
F14 t
d(clkH-wen)
Delay time, output clock gpmc_clk rising edge to output write I
(9)
– 2.3 I
(9)
+ 4.5 ns
enable gpmc_wen transition
F15 t
d(clkH-do)
Delay time, output clock gpmc_clk rising edge to output data J
(10)
– 2.3 J
(10)
+ 1.9 ns
gpmc_ad[15:0] transition
F17 t
d(clkH-be[x]n)
Delay time, output clock gpmc_clk rising edge to output lower J
(10)
– 2.3 J
(10)
+ 1.9 ns
byte enable and command latch enable gpmc_be0n_cle
transition
F18 t
w(csnV)
Pulse duration, output chip select gpmc_csn[x]
(11)
Read A
(1)
ns
low
Write A
(1)
ns
F19 t
w(be[x]nV)
Pulse duration, output lower byte enable and Read C
(3)
ns
command latch enable gpmc_be0n_cle, output
Write C
(3)
ns
upper byte enable gpmc_be1n low
F20 t
w(advnV)
Pulse duration, output address valid and address Read K
(13)
ns
latch enable gpmc_advn_ale low
Write K
(13)
ns
(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(14)
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(14)
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(14)
With n being the page burst access number.
(2) B = ClkActivationTime * GPMC_FCLK
(14)
(3) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
(14)
For burst read: C = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(14)
For burst write: C = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(14)
With n being the page burst access number.
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