Datasheet

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AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717E –OCTOBER 2011–REVISED JANUARY 2013 www.ti.com
5.5 External Memory Interfaces
The device includes the following external memory interfaces:
• General-purpose memory controller (GPMC)
• mDDR(LPDDR), DDR2, DDR3, DDR3L Memory Interface (EMIF)
5.5.1 General-Purpose Memory Controller (GPMC)
NOTE
For more information, see the Memory Subsystem and General-Purpose Memory Controller
section of the AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference
Manual (literature number SPRUH73).
The GPMC is the unified memory controller used to interface external memory devices such as:
• Asynchronous SRAM-like memories and ASIC devices
• Asynchronous page mode and synchronous burst NOR flash
• NAND flash
5.5.1.1 GPMC and NOR Flash—Synchronous Mode
Synchronous mode is not supported for OPP50.
Table 5-19 and Table 5-20 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-16 through Figure 5-20).
Table 5-18. GPMC and NOR Flash Timing Conditions—Synchronous Mode
TIMING CONDITION PARAMETER MIN TYP MAX UNIT
Input Conditions
t
R
Input signal rise time 1 5 ns
t
F
Input signal fall time 1 5 ns
Output Condition
C
LOAD
Output load capacitance 3 30 pF
Table 5-19. GPMC and NOR Flash Timing Requirements—Synchronous Mode
OPP100
NO. UNIT
MIN MAX
F12 t
su(dV-clkH)
Setup time, input data gpmc_ad[15:0] valid before output clock gpmc_clk 3.2 ns
high
F13 t
h(clkH-dV)
Hold time, input data gpmc_ad[15:0] valid after output clock gpmc_clk high 2.5 ns
F21 t
su(waitV-clkH)
Setup time, input wait gpmc_wait[x]
(1)
valid before output clock gpmc_clk 3.2 ns
high
F22 t
h(clkH-waitV)
Hold time, input wait gpmc_wait[x]
(1)
valid after output clock gpmc_clk high 2.5 ns
(1) In gpmc_wait[x], x is equal to 0 or 1.
122 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated
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