Datasheet

PRODUCTPREVIEW
RGMII[x]_TCLK
(A)
RGMII[x]_TD[3:0]
(B)
RGMII[x]_TCTL
(B)
1
1st Half-byte
TXERRTXEN
2nd Half-byte
1
2
RGMII[x]_TCLK
4
4
2
3
1
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com SPRS717E –OCTOBER 2011–REVISED JANUARY 2013
Table 5-16. Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
(see Figure 5-14)
10 Mbps 100 Mbps 1000 Mbps
NO. PARAMETER UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
1 t
c(TXC)
Cycle time, TXC 360 440 36 44 7.2 8.8 ns
Pulse duration, TXC
2 t
w(TXCH)
160 240 16 24 3.6 4.4 ns
high
3 t
w(TXCL)
Pulse duration, TXC low 160 240 16 24 3.6 4.4 ns
4 t
t(TXC)
Transition time, TXC 0.75 0.75 0.75 ns
Figure 5-14. RGMII[x]_TCLK Timing - RGMII Mode
Table 5-17. Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
(see Figure 5-15)
10 Mbps 100 Mbps 1000 Mbps
NO. PARAMETER UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
t
sk(TD-TXC)
TD to TXC output skew -0.5 0.5 -0.5 0.5 -0.5 0.5
1 ns
t
sk(TX_CTL-TXC)
TX_CTL to TXC output skew -0.5 0.5 -0.5 0.5 -0.5 0.5
t
t(TD)
Transition time, TD 0.75 0.75 0.75
2 ns
t
t(TX_CTL)
Transition time, TX_CTL 0.75 0.75 0.75
A. The Ethernet MAC and switch implemented in the AM335x device supports internal delay mode, but timing closure
was not performed for this mode of operation. Therefore, the AM335x device does not support internal delay mode.
B. Data and control information is transmitted using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on
the rising edge of RGMII[x]_TCLK and data bits 7-4 on the falling edge of RGMII[x]_TCLK. Similarly, RGMII[x]_TCTL
carries TXEN on rising edge of RGMII[x]_TCLK and TXERR of falling edge of RGMII[x]_TCLK.
Figure 5-15. RGMII[x]_TD[3:0], RGMII[x]_TCTL Timing - RGMII Mode
Copyright © 2011–2013, Texas Instruments Incorporated Peripheral Information and Timings 121
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