Datasheet

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RGMII[x]_RD[3:0]
(B)
RGMII[x]_RCTL
(B)
RGMII[x]_RCLK
(A)
1
RXERR
1st Half-byte
2nd Half-byte
2
3
RXDV
RGRXD[3:0] RGRXD[7:4]
RGMII[x]_RCLK
2
3
1
4
4
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717E –OCTOBER 2011–REVISED JANUARY 2013 www.ti.com
5.4.1.4 Ethernet MAC and Switch RGMII Electrical Data and Timing
Table 5-14. Timing Requirements for RGMII[x]_RCLK - RGMII Mode
(see Figure 5-12)
10 Mbps 100 Mbps 1000 Mbps
NO. UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
1 t
c(RXC)
Cycle time, RXC 360 440 36 44 7.2 8.8 ns
Pulse duration, RXC
2 t
w(RXCH)
160 240 16 24 3.6 4.4 ns
high
3 t
w(RXCL)
Pulse duration, RXC low 160 240 16 24 3.6 4.4 ns
4 t
t(RXC)
Transition time, RXC 0.75 0.75 0.75 ns
Figure 5-12. RGMII[x]_RCLK Timing - RGMII Mode
Table 5-15. Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
(see Figure 5-13)
10 Mbps 100 Mbps 1000 Mbps
NO. UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Setup time, RD[3:0] valid
t
su(RD-RXC)
1 1 1
before RXC high or low
1 ns
Setup time, RX_CTL valid
t
su(RX_CTL-RXC)
1 1 1
before RXC high or low
Hold time, RD[3:0] valid
t
h(RXC-RD)
1 1 1
after RXC high or low
2 ns
Hold time, RX_CTL valid
t
h(RXC-RX_CTL)
1 1 1
after RXC high or low
t
t(RD)
Transition time, RD 0.75 0.75 0.75
3 ns
t
t(RX_CTL)
Transition time, RX_CTL 0.75 0.75 0.75
A. RGMII[x]_RCLK must be externally delayed relative to the RGMII[x]_RD[3:0] and RGMII[x]_RCTL signals to meet the
respective timing requirements.
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the
rising edge of RGMII[x]_RCLK and data bits 7-4 on the falling edge of RGMII[x]_RCLK. Similarly, RGMII[x]_RCTL
carries RXDV on rising edge of RGMII[x]_RCLK and RXERR on falling edge of RGMII[x]_RCLK.
Figure 5-13. RGMII[x]_RD[3:0], RGMII[x]_RCTL Timing - RGMII Mode
120 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated
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