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GMII[x]_RXCLK
2
3
1
4
4
1
MDIO_CLK (Output)
MDIO_DATA (Output)
MDIO_CLK
2
3
1
4
4
AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com SPRS717E –OCTOBER 2011–REVISED JANUARY 2013
Figure 5-3. MDIO_CLK Timing
Table 5-6. Switching Characteristics for MDIO_DATA
(see Figure 5-4)
NO. PARAMETER MIN TYP MAX UNIT
1 t
d(MDC-MDIO)
Delay time, MDC high to MDIO valid 10 390 ns
Figure 5-4. MDIO_DATA Timing - Output Mode
5.4.1.2 Ethernet MAC and Switch MII Electrical Data and Timing
Table 5-7. Timing Requirements for GMII[x]_RXCLK - MII Mode
(see Figure 5-5)
10 Mbps 100 Mbps
NO. UNIT
MIN TYP MAX MIN TYP MAX
1 t
c(RX_CLK)
Cycle time, RX_CLK 399.96 400.04 39.996 40.004 ns
2 t
w(RX_CLKH)
Pulse Duration, RX_CLK high 140 260 14 26 ns
3 t
w(RX_CLKL)
Pulse Duration, RX_CLK low 140 260 14 26 ns
4 t
t(RX_CLK)
Transition time, RX_CLK 5 5 ns
Figure 5-5. GMII[x]_RXCLK Timing - MII Mode
Copyright © 2011–2013, Texas Instruments Incorporated Peripheral Information and Timings 115
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