Datasheet

The general setup tab includes

controls for the digital TX interface

This section controls the setup of the digital

interface as well as the TX interpolation

DCLK

Data

Initial EVM Setup and Basic Test Procedure

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The data coming from the TSW1400 is edge aligned while the AFE722x expects the serial LVDS data to

arrive edge centered. Here the programmable clock delay inside the AFE722x can be used to delay the

edge-aligned clock closer towards the center of the data.

Table 2 shows clock delays for DAC sampling rates that showed proper operation.

Table 2. Clock Delays for Listed DAC Sampling Rates

DAC Sampling Rate Suitable Clock Delay

130 Msps 0 ps to 900 ps

122.88 Msps 0 ps to 900 ps

100 Msps 0 ps to 1.2 ns

80 Msps 0 ps to 1.8 ns

65 Msps 0 ps to 2.1 ns

40 Msps 0 ps to 2.1 ns

Figure 6.

For TX, the output data of the TSW1400 needs to be properly configured for 6× serialization using High

Speed Data Converter Pro.

1. Install the latest High Speed Data Converter Pro GUI Installer from www.ti.com/tool/tsw1400evm

2. Open High Speed Data Converter Pro GUI

3. Enter Data Rate to DAC

4. Enter Tone BW, # and Tone Center frequency

5. Ensure match on data format between TSW1400 and AFE722x

AFE722x Evaluation Module (AFE722xEVM) User's Guide SLOU362–February 2013

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