Datasheet

www.ti.com Initial EVM Setup and Basic Test Procedure
Figure 5. HSDCP Settings
4.3 TX Path Using TSW1400
Configure the AFE722x digital interface to match the serial LVDS interface from the TSW1400.
In the General Setup tab of the AFE722x programming software, set the control registers as shown in
Table 1. Also, the USB communication warning sign should be monitored after the USB reset to ensure
proper communication with the AFE722x EVM.
Table 1. Control Registers
Register Bit Setting
Interface Serial LVDS
Master Override Enabled
Serial LVDS 2 Wire
Data Orientation MSB first
Format 2s Complement
Clock Delay Enabled
Clock Delay 300 ps
Frame Clock Delay Disabled
Frame Clock Delay 0 ps
7
SLOU362–February 2013 AFE722x Evaluation Module (AFE722xEVM) User's Guide
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