Datasheet

The section controls the setup of the digital

interface as well as test modes and digital

features such as decimation and loopback

The general setup tab includes

controls for the digital RX interface

RX Setup

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6.6 Decimation on the ADC

On the receive channels of the AFE722x, the output can be decimated by 2x using the on-chip FIR

halfband filter. This has no impact on the clock requirements to the AFE722x – it merely reduces the

output data rate by a factor of 2x and settings (sampling and input frequency) on the TSW1400 capture

card or other data capture tool need to be adjusted accordingly.

7 RX Setup

The RX section of the AFE722x is controlled on two

separate tabs of the EVM software.

In the ‘General Setup’ tab are the control registers for

the digital interface such as CMOS or serial LVDS

output, for example. In order to use the TSW1400 to

capture the received data, the following register settings

are required:

Interface Serial LVDS

Master Override Enabled

Format Offset Binary

Serial LVDS 2 Wire

Data Orientation MSB First

DSR Mode Disabled

Wordwise Output Disabled

Bitwise RX Disabled

Halfrx in 2wire Disabled

This tab also controls the register to set the digital

interface to test pattern mode and custom patterns can

be loaded as well. Furthermore RX decimation settings

as well as TX RX loopback mode are controlled here as

well.

AFE722x Evaluation Module (AFE722xEVM) User's Guide SLOU362–February 2013

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