Datasheet

Clocking Configuration

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The CDCE72010 clock buffer on the AFE722x is used to provide the clock to the TSW1400. Additional

dividers can be added to the clock output in order to divide the clock appropriately for optional

interpolation by 2x or 4x.

Figure 10. Configuration of Clock Output in CDCE72010

Preconfigured setup files:

AUX IN – INT2x – div3 AFE div8 ext 3x clock to CDC AUX IN (see Section 6.5)

TSW.txt

AUX IN – div3 AFE div4 TSW.txt ext 3x clock to CDC AUX IN (see Section 6.1)

REF IN (10MHz) – div6 AFE div8 ext 10MHz clock on REF IN (see Section 6.2)

TSW.txt

REF IN (10MHz) – INT2x – div6 AFE ext 10MHz clock on REF IN (see Section 6.2/Section 6.5)

div16 TSW.txt

REF IN (122.88MHz) – div6 AFE div8 ext 122.88MHz clock on REF IN

TSW.txt (see Section 6.2)

6.1 Non-VCXO Option (Default)

This setup is the default configuration and provides the

option to operate AFE722x and TSW1400 synchronous at

any arbitrary sampling rate without the use of a VCXO.

This setup is useful for testing the AFE722x at clock

frequencies where a VCXO is not immediately available.

AFE722x Evaluation Module (AFE722xEVM) User's Guide SLOU362–February 2013

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