User's Guide SLOU362 – February 2013 AFE722x Evaluation Module (AFE722xEVM) User's Guide The AFE722x EVM includes a great level of flexibility enabling testing in a more system-like environment. The individual power rails can be generated through LDOs or DC/DC converters from a 6-V power source and the EVM clock architecture allows for external clock input as well as clock generation using a low-jitter PLL in combination with a VCXO.
Software Installation 1 2 3 4 5 6 7 8 www.ti.com Contents Software Installation ........................................................................................................ 2 AFE722x.ini file for TSW140x ............................................................................................. 3 AFE722x EVM Software - SPI Control ................................................................................... 3 Initial EVM Setup and Basic Test Procedure ...............................
AFE722x.ini file for TSW140x www.ti.com Figure 1. Software Installation Screens 2 AFE722x.ini file for TSW140x The AFE722xEVM software package comes with new ini files for the TSW140x. These AFE722x.ini files (AFE722x_ADC.ini for TSW1400/TSW1405 and AFE722x_DAC.
Initial EVM Setup and Basic Test Procedure Tabs to control basic setup, RX and TX & SYNC registers as well as CDCE72010 www.ti.com Reset USB port on FTDI chip – required after power up of AFE722x EVM. Control to send or read all registers (AFE722x and CDCE72010) as well as load or save register files. Individual control registers Warning indication that USB communication is not established.
Initial EVM Setup and Basic Test Procedure www.ti.com Figure 3. AFE722x EVM Setup 4.1 CDCE72010 Configuration The initial EVM setup is configured so that the AFE722x can be operated at any desired sampling rate. Since the TSW1400 requires an external clock at ¾ of the AFE clock rate (see clocking section) the external clock applied to the CDC AUX IN connector needs to be 3× the AFE sampling rate (that is, 368.64 MHz for 122.88-MHz operation).
Initial EVM Setup and Basic Test Procedure www.ti.
Initial EVM Setup and Basic Test Procedure www.ti.com Figure 5. HSDCP Settings 4.3 TX Path Using TSW1400 Configure the AFE722x digital interface to match the serial LVDS interface from the TSW1400. In the General Setup tab of the AFE722x programming software, set the control registers as shown in Table 1. Also, the USB communication warning sign should be monitored after the USB reset to ensure proper communication with the AFE722x EVM. Table 1.
Initial EVM Setup and Basic Test Procedure www.ti.com The data coming from the TSW1400 is edge aligned while the AFE722x expects the serial LVDS data to arrive edge centered. Here the programmable clock delay inside the AFE722x can be used to delay the edge-aligned clock closer towards the center of the data. DCLK Data Table 2 shows clock delays for DAC sampling rates that showed proper operation. Table 2.
Initial EVM Setup and Basic Test Procedure www.ti.com 6. Select Create Tones 7. Press the Send button Figure 7. The DAC output should show something like Figure 8 on the spectrum analyzer.
Initial EVM Setup and Basic Test Procedure www.ti.com Figure 8. Spectrum Analyzer: Sample Rate = 245.
Power Supply Options www.ti.com 5 Power Supply Options The AFE722x EVM is designed to operate from an external 6-V wall wart supply. An LDO generates a 5-V rail for the TRF3703 IQ modulator as well as for the low-noise LDOs, which are generating a 3.3-V and 1.8-V rail for the AFE722x and the CDCE72010. Alternatively, the 3.3-V and 1.8-V rails can be generated using DC/DC converters which operate directly from the 6-V input for maximum power efficiency.
Clocking Configuration www.ti.com The CDCE72010 clock buffer on the AFE722x is used to provide the clock to the TSW1400. Additional dividers can be added to the clock output in order to divide the clock appropriately for optional interpolation by 2x or 4x. Figure 10. Configuration of Clock Output in CDCE72010 Preconfigured setup files: AUX IN – INT2x – div3 AFE div8 TSW.txt AUX IN – div3 AFE div4 TSW.txt REF IN (10MHz) – div6 AFE div8 TSW.txt REF IN (10MHz) – INT2x – div6 AFE div16 TSW.txt REF IN (122.
Clocking Configuration www.ti.com 6.2 System Level In this system configuration on the EVM a VCXO at 6x the desired clock frequency is required – alternatively a different VCXO frequency can be used and the internal CDCE72010 dividers adjusted accordingly. An external reference can be locked to the VCXO for coherency using the CDCE72010. In this configuration the CDCE72010 provides a /6 copy of the VCXO to the AFE722x clock input as well as a /8 copy to the TSW1400.
RX Setup 6.6 www.ti.com Decimation on the ADC On the receive channels of the AFE722x, the output can be decimated by 2x using the on-chip FIR halfband filter. This has no impact on the clock requirements to the AFE722x – it merely reduces the output data rate by a factor of 2x and settings (sampling and input frequency) on the TSW1400 capture card or other data capture tool need to be adjusted accordingly. 7 RX Setup The RX section of the AFE722x is controlled on two separate tabs of the EVM software.
TX Setup www.ti.com The other portion of the RX setup is located on the Receive Control tab which includes register access for the mixing stage, power meter, and power options for the digital RX section. Also, the auxiliary ADC registers are configured on this tab.
TX Setup www.ti.com R46 0S SMA Connector DAC A R56 0S R127 DNI R133 DNI SMA Connector LO Fc=125 MHz TRF3703 RF Out SMA Connector R114 DNI R120 DNI SMA Connector R58 0S DAC B R68 0S Figure 12. AFE722x Schematic When using the TSW1400 as a pattern generator for the AFE722x, first the digital interface needs to be configured to match the serial LVDS interface from the TSW1400. The following control registers need to be set in the General Setup tab of the AFE722x programming software.
TX Setup www.ti.com The data coming from the TSW1400 is edge aligned while the AFE722x expects the serial LVDS data to arrive edge centered. Here the programmable clock delay can be used to delay the edge-aligned clock closer towards the center of the data. The table below shows clock delays for the listed DAC sampling rates that showed proper operation:. DAC Sampling Rate 130 Msps 122.88 Msps 100 Msps 80 Msps 65 Msps 40 Msps DCLK Data Suitable Clock Delay 0 ps to 900 ps 0 ps to 900 ps 0 ps to 1.
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods.
FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
【Important Notice for Users of this Product in Japan】 】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.
EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.