Datasheet

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Board Configuration

Table 3. CW Mode, ADC Clock

Clock Reference

Description

Type Designator

J9/J10 External CW Mode clock. The default is using onboard oscillator.

CW output for I-channel via an external operational amplifier. The EVM has converted the

differential signal CW_IP_OUTP and CW_IP_OUTM into this single-ended output through an

J12

operational amplifier.

JP52/JP53

To observe CW_IP_OUTP and CW_IP_OUTM before the external operational amplifier, probe

JP52 and JP53.

CW Mode

CW output for V-channel via an external operational amplifier. The EVM has converted the

differential signal CW_VP_OUTP and CW_VP_OUTM into this single-ended output through an

J13

operational amplifier.

JP56/JP57

To observe CW_VP_OUTP and CW_VP_OUTM before the external operational amplifier, probe

JP56 and JP57.

JX1 This connector shows the signals of J12 and J13 simultaneously.

JP9 selects on_board_ADC CMOS clock or external clock from J14. Default setup in Figure 19

uses onboard CMOS clock. Set it to the other side to use the external clock source.

JP9/JP10

ADC

Short to power up onboard CMOS clock

J14 External ADC clock Input

11.3 Vcntl Control Input

Figure 28. Vcntl

Table 4. CW Mode and Vcntl

Connector Description

JP15 Choose onboard Vcntl or external Vcntl. The default setup uses onboard Vcntl.

J14 External Vcntl input. The range is from 0 V to 1.5 V.

VR2 Onboard Vcntl adjustment. Use JP15 pin 3 which has the text On-Board to monitor the Vcntl voltage level.

SLOU338A–October 2012–Revised November 2012 AFE5809EVM Evaluation Module

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