Datasheet

AFE5808

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SLOS688C –SEPTEMBER 2010–REVISED APRIL 2012

Complete Power-Down Mode

To achieve the lowest power dissipation of 0.7 mW/CH, the AFE5808 can be placed into a complete power-down

mode. This mode is controlled through the registers ADC_COMPLETE_PDN, VCA_COMPLETE_PDN or

PDN_GLOBAL pin. In the complete power-down mode, all circuits including reference circuits within the

AFE5808 are powered down; and the capacitors connected to the AFE5808 are discharged. The wake-up time

depends on the time needed to recharge these capacitors. The wake-up time depends on the time that the

AFE5808 spends in shutdown mode. 0.1μF at INP and 15nF at INM can give a wake-up time close to 2.5ms

Power Saving in CW Mode

Usually only half the number of channels in a system are active in the CW mode. Thus the individual channel

control through ADC_PDN_CH <7:0> and VCA_PDN_CH <7:0> can power down unused channels and save

power consumption greatly. Under the default register setting in the CW mode, the voltage controlled attenuator,

PGA, and ADC are still active. During the debug phase, both the PW and CW paths can be running

simultaneously. In real operation, these blocks need to be powered down manually.

TEST MODES

The AFE5808 includes multiple test modes to accelerate system development. The ADC test modes have been

discussed in the register description section.

The VCA has a test mode in which the CH7 and CH8 PGA outputs can be brought to the CW pins. By monitoring

these PGA outputs, the functionality of VCA operation can be verified. The PGA outputs are connected to the

virtual ground pins of the summing amplifier (CW_IP_AMPINM/P, CW_QP_AMPINM/P) through 5KΩ resistors.

The PGA outputs can be monitored at the summing amplifier outputs when the LPF capacitors C

EXT

are

removed. Please note that the signals at the summing amplifier outputs are attenuated due to the 5KΩ resistors.

The attenuation coefficient is R

INT/EXT

/5KΩ

If users would like to check the PGA outputs without removing CEXT, an alternative way is to measure the PGA

outputs directly at the CW_IP_AMPINM/P and CW_QP_AMPINM/P when the CW summing amplifier is powered

down

Some registers are related to this test mode. PGA Test Mode Enable: Reg59[9]; Buffer Amplifier Power Down

Reg59[8]; and Buffer Amplifier Gain Control Reg54[4:0]. Based on the buffer amplifier configuration, the registers

can be set in different ways:

Configuration 1:

In this configuration, the test outputs can be monitored at CW_AMPINP/M

• Reg59[9]=1 ;Test mode enabled

• Reg59[8]=0 ;Buffer amplifier powered down

Configuration 2:

In this configuration, the test outputs can be monitored at CW_OUTP/M

• Reg59[9]=1 ;Test mode enabled

• Reg59[8]=1 ;Buffer amplifier powered on

• Reg54[4:0]=10H; Internal feedback 2K resistor enabled. Different values can be used as well

Product Folder Links: AFE5808