Datasheet

AFE5808
SLOS688C –SEPTEMBER 2010–REVISED APRIL 2012 www.ti.com
As discussed in the theory of operation, the attenuator architecture uses seven attenuator segments that are
equally spaced in order to approximate the linear-in-dB gain-control slope. This approximation results in a
monotonic slope; the gain ripple is typically less than ±0.5dB.
The control voltage input (V
CNTLM/P
pins) represents a high-impedance input. The V
CNTLM/P
pins of multiple
AFE5808 devices can be connected in parallel with no significant loading effects. When the voltage level (V
CNTLP
-
V
CNTLM
) is above 1.5V or below 0V, the attenuator continues to operate at its maximum attenuation level or
minimum attenuation level respectively. It is recommended to limit the voltage from -0.3V to 2V.
When the AFE5808 operates in CW mode, the attenuator stage remains connected to the LNA outputs.
Therefore, it is recommended to power down the VCA using the PDN_VCA register bit. In this case, V
CNTLP
-
V
CNTLM
voltage does not matter.
The AFE5808 gain-control input has a –3dB bandwidth of approximately 800KHz. This wide bandwidth, although
useful in many applications (e.g. fast V
CNTL
response), can also allow high-frequency noise to modulate the gain
control input and finally affect the Doppler performance. In practice, this modulation can easily be avoided by
additional external filtering (RV
CNTL
and CV
CNTL
) at V
CNTLM/P
pins as Figure 80 shows. However, the external
filter's cutoff frequency cannot be kept too low as this results in low gain response time. Without external filtering,
the gain control response time is typically less than 1 μs to settle within 10% of the final signal level of 1VPP
(–6dBFS) output as indicated in Figure 51 and Figure 52.
Typical V
CNTLM/P
signals are generated by an 8bit to 12bit 10MSPS digital to analog converter (DAC) and a
differential operation amplifier. TI’s DACs, such as TLV5626 and DAC7821/11 (10MSPS/12bit), could be used to
generate TGC control waveforms. Differential amplifiers with output common mode voltage control (e.g.
THS4130 and OPA1632) can connect the DAC to the V
CNTLM/P
pins. The buffer amplifier can also be configured
as an active filter to suppress low frequency noise. More information can be found in the literatures SLOS318F
and SBAA150. The V
CNTL
vs Gain curves can be found in Figure 2. The below table also shows the absolute
gain vs. V
CNTL
, which may help program DAC correspondingly.
In PW Doppler and color Doppler modes, V
CNTL
noise should be minimized to achieve the best close-in phase
noise and SNR. Digital V
CNTL
feature is implemented to address this need in the AFE5808. In the digital V
CNTL
mode, no external V
CNTL
is needed.
Table 12. V
CNTLP
–V
CNTLM
vs Gain Under Different LNA and PGA Gain Settings (Low Noise Mode)
Gain (dB) Gain (dB) Gain (dB) Gain (dB) Gain (dB) Gain (dB)
V
CNTLP
–V
CNTLM
LNA = 12 dB LNA = 18 dB LNA = 24 dB LNA = 12 dB LNA = 18 dB LNA = 24 dB
(V)
PGA = 24 dB PGA = 24 dB PGA = 24 dB PGA = 30 dB PGA = 30 dB PGA = 30 dB
0 36.45 42.45 48.45 42.25 48.25 54.25
0.1 33.91 39.91 45.91 39.71 45.71 51.71
0.2 30.78 36.78 42.78 36.58 42.58 48.58
0.3 27.39 33.39 39.39 33.19 39.19 45.19
0.4 23.74 29.74 35.74 29.54 35.54 41.54
0.5 20.69 26.69 32.69 26.49 32.49 38.49
0.6 17.11 23.11 29.11 22.91 28.91 34.91
0.7 13.54 19.54 25.54 19.34 25.34 31.34
0.8 10.27 16.27 22.27 16.07 22.07 28.07
0.9 6.48 12.48 18.48 12.28 18.28 24.28
1.0 3.16 9.16 15.16 8.96 14.96 20.96
1.1 –0.35 5.65 11.65 5.45 11.45 17.45
1.2 –2.48 3.52 9.52 3.32 9.32 15.32
1.3 –3.58 2.42 8.42 2.22 8.22 14.22
1.4 –4.01 1.99 7.99 1.79 7.79 13.79
1.5 –4 2 8 1.8 7.8 13.8
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