Datasheet

AFE5808
www.ti.com SLOS688C –SEPTEMBER 2010–REVISED APRIL 2012
PIN FUNCTIONS (continued)
PIN
DESCRIPTION
NO. NAME
Positive differential input of the In-phase summing amplifier. External LPF capacitor has to be
E1 CW_IP_AMPINP connected between CW_IP_AMPINP and CW_IP_OUTM. This pin becomes the CH7 PGA positive
output when PGA test mode is enabled. Can be floated if not used.
Negative differential output for the In-phase summing amplifier. External LPF capacitor has to be
F1 CW_IP_OUTM
connected between CW_IP_AMPINP and CW_IP_OUTPM. Can be floated if not used.
Positive differential output for the In-phase summing amplifier. External LPF capacitor has to be
F2 CW_IP_OUTP
connected between CW_IP_AMPINM and CW_IP_OUTP. Can be floated if not used.
Negative differential input of the quadrature-phase summing amplifier. External LPF capacitor has to
CW_QP_AMPIN
J2 be connected between CW_QP_AMPINM and CW_QP_OUTP. This pin becomes CH8 PGA negative
M
output when PGA test mode is enabled. Can be floated if not used.
Positive differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be
J1 CW_QP_AMPINP connected between CW_QP_AMPINP and CW_QP_OUTM. This pin becomes CH8 PGA positive
output when PGA test mode is enabled. Can be floated if not used.
Negative differential output for the quadrature-phase summing amplifier. External LPF capacitor has to
H1 CW_QP_OUTM
be connected between CW_QP_AMPINP and CW_QP_OUTM. Can be floated if not used.
Positive differential output for the quadrature-phase summing amplifier. External LPF capacitor has to
H2 CW_QP_OUTP
be connected between CW_QP_AMPINM and CW_QP_OUTP. Can be floated if not used.
N8, P9~P7,
D1M~D8M ADC CH1~8 LVDS negative outputs
P3~P1, N2
N9, R9~R7,
D1P~D8P ADC CH1~8 LVDS positive outputs
R3~R1, N1
P6 DCLKM LVDS bit clock (7x) negative output
R6 DCLKP LVDS bit clock (7x) positive output
K7,
L5~L7,M5~M8, DNC Do not connect. Must leave floated
N4, N6
N3, N7 DVDD ADC digital and I/O power supply, 1.8V
N5, P5, R5 DVSS ADC digital ground
P4 FCLKM LVDS frame clock (1X) negative output
R4 FCLKP LVDS frame clock (1X) positive output
CH1~8 complimentary analog inputs. Bypass to ground with ≥ 0.015µF capacitors. The HPF response
C9~C2 INM1…INM8
of the LNA depends on the capacitors.
A9~A2 INP1...INP8 CH1~8 analog inputs. AC couple to inputs with ≥ 0.1µF capacitors.
L8 PDN_ADC ADC partial (fast) power down control pin with an internal pull down resistor of 100kΩ. Active High.
J8 PDN_VCA VCA partial (fast) power down control pin with an internal pull down resistor of 20kΩ. Active High.
Global (complete) power-down control pin for the entire chip with an internal pull down resistor of
H8 PDN_GLOBAL
20kΩ. Active High.
0.5V reference output in the internal reference mode. Must leave floated in the internal reference
L4 REFM
mode. Adding a test point on the PCB is recommended for monitoring the reference output.
1.5V reference output in the internal reference mode. Must leave floated in the internal reference
M4 REFP
mode. Adding a test point on the PCB is recommended for monitoring the reference output.
H9 RESET Hardware reset pin with an internal pull-down resistor of 20kΩ. Active high.
J9 SCLK Serial interface clock input with an internal pull-down resistor of 20kΩ
K9 SDATA Serial interface data input with an internal pull-down resistor of 20kΩ
M9 SDOUT Serial interface data readout. High impedance when readout is disabled.
L9 SEN Serial interface enable with an internal pull up resistor of 20kΩ. Active low.
K4 VCNTLM Negative differential attenuation control pin.
K3 VCNTLP Positive differential attenuation control pin
K5 VHIGH Bias voltage; bypass to ground with ≥1µF.
M3 VREF_IN ADC 1.4V reference input in the external reference mode; bypass to ground with 0.1µF.
K7, L5~L7,
M5~M8, N4, DNC Do not connect. Must leave floated
N6
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