Datasheet

AFE5808
SLOS688C –SEPTEMBER 2010–REVISED APRIL 2012 www.ti.com
Table 4. VCA Register Map (continued)
ADDRESS ADDRESS Default
FUNCTION DESCRIPTION
(DEC) (HEX) Value
53[7:0] 0x35[7:0] 0 PDN_CH<7:0> 0: Normal operation;
1: Powers down corresponding channels. Bit7→CH8,
Bit6→CH7…Bit0→CH1. PDN_CH will shut down whichever
blocks are active depending on TGC mode or CW mode
53[8] 0x35[8] 0 RESERVED Set to 0
53[9] 0x35[9] 0 RESERVED Set to 0
53[10] 0x35[10] 0 LOW_POWER 0: Low noise mode;
1: Sets to low power mode (53[11]=0). At 30dB PGA, total
chain gain may slightly change.
See typical characteristics
53[11] 0x35[11] 0 MED_POWER 0: Low noise mode;
1: Sets to medium power mode(53[10]=0). At 30dB PGA, total
chain gain may slightly change.
See typical characteristics
53[12] 0x35[12] 0 PDN_VCAT_PGA 0: Normal operation;
1: Powers down VCAT (voltage-controlled-attenuator) and PGA
53[13] 0x35[13] 0 PDN_LNA 0: Normal operation;
1: Powers down LNA only
53[14] 0x35[14] 0 VCA_PARTIAL_PDN 0: Normal operation;
1: Powers down LNA, VCAT, and PGA partially(fast wake
response)
53[15] 0x35[15] 0 VCA_COMPLETE_PDN 0: Normal operation;
1: Powers down LNA, VCAT, and PGA completely (slow wake
response). This bit can overwrite 53[14].
54[4:0] 0x36[4:0] 0 CW_SUM_AMP_GAIN_CNTL Selects Feedback resistor for the CW Amplifier as per Table 6
below
54[5] 0x36[5] 0 CW_16X_CLK_SEL 0: Accepts differential clock;
1: Accepts CMOS clock
54[6] 0x36[6] 0 CW_1X_CLK_SEL 0: Accepts CMOS clock;
1: Accepts differential clock
54[7] 0x36[7] 0 RESERVED Set to 0
54[8] 0x36[8] 0 CW_TGC_SEL 0: TGC Mode;
1 : CW Mode
Note : VCAT and PGA are still working in CW mode. They
should be powered down separately through 53[12]
54[9] 0x36[9] 0 CW_SUM_AMP_ENABLE 0: enables CW summing amplifier;
1: disables CW summing amplifier
Note: 54[9] is only effective in CW mode.
54[11:10] 0x36[11:1 0 CW_CLK_MODE_SEL 00: 16X mode;
0]
01: 8X mode;
10: 4X mode;
11: 1X mode
55[3:0] 0x37[3:0] 0 CH1_CW_MIXER_PHASE
55[7:4] 0x37[7:4] 0 CH2_CW_MIXER_PHASE
55[11:8] 0x37[11:8] 0 CH3_CW_MIXER_PHASE
55[15:12] 0x37[15:1 0 CH4_CW_MIXER_PHASE
2]
0000→1111, 16 different phase delays, see Table 9
56[3:0] 0x38[3:0] 0 CH5_CW_MIXER_PHASE
56[7:4] 0x38[7:4] 0 CH6_CW_MIXER_PHASE
56[11:8] 0x38[11:8] 0 CH7_CW_MIXER_PHASE
56[15:12] 0x38[15:1 0 CH8_CW_MIXER_PHASE
2]
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