Datasheet

AFE5808

SLOS688C –SEPTEMBER 2010–REVISED APRIL 2012

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TEST_PATTERN_MODES: Address: 2[15:13]

The AFE5808 can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal

ADC data output. The device may also be made to output 6 preset patterns:

1. Ramp: Setting Register 2[15:13]=111causes all the channels to output a repeating full-scale ramp pattern.

The ramp increments from zero code to full-scale code in steps of 1LSB every clock cycle. After hitting the

full-scale code, it returns back to zero code and ramps again.

2. Zeros: The device can be programmed to output all zeros by setting Register 2[15:13]=110;

3. Ones: The device can be programmed to output all 1s by setting Register 2[15:13]=100;

4. Deskew Patten: When 2[15:13]=010; this mode replaces the 14-bit ADC output with the 01010101010101

word.

5. Sync Pattern: When 2[15:13]=001, the normal ADC output is replaced by a fixed 11111110000000 word.

6. Toggle: When 2[15:13]=101, the normal ADC output is alternating between 1's and 0's. The start state of

ADC word can be either 1's or 0's.

7. Custom Pattern: It can be enabled when 2[15:13]=011;. Users can write the required VALUE into register

bits <CUSTOM PATTERN> which is Register 5[13:0]. Then the device will output VALUE at its outputs,

about 3 to 4 ADC clock cycles after the 24th rising edge of SCLK. So, the time taken to write one value is 24

SCLK clock cycles + 4 ADC clock cycles. To change the customer pattern value, users can repeat writing

not be high. For example, 128 points custom pattern will take approximately 128 x (24 SCLK clock cycles + 4

ADC clock cycles).

NOTE

only one of the above patterns can be active at any given instant.

Product Folder Links: AFE5808