Datasheet

AFE5808

www.ti.com

SLOS688C –SEPTEMBER 2010–REVISED APRIL 2012

Table 3. Digital HPF –1dB Corner Frequency vs. K and Fs

k 40 MSPS 50 MSPS 65 MSPS

2 2780 KHz 3480 KHz 4520 KHz

3 1490 KHz 1860 KHz 2420 KHz

4 770 KHz 960 KHz 1250 KHz

LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]

The low-frequency noise suppression mode is especially useful in applications where good noise performance is

desired in the frequency band of 0MHz to 1MHz (around dc). Setting this mode shifts the low-frequency noise of

the AFE5808 to approximately Fs/2, thereby moving the noise floor around dc to a much lower value. Register bit

1[11] is used for enabling or disabling this feature. When this feature is enabled, power consumption of the

device will be increased slightly by approximate 1mW/CH.

LVDS_OUTPUT_RATE_2X: Address: 1[14]

The output data always uses a DDR format, with valid/different bits on the positive as well as the negative edges

of the LVDS bit clock, DCLK. The output rate is set by default to 1X (LVDS_OUTPUT_RATE_2X = 0), where

each ADC has one LVDS stream associated with it. If the sampling rate is low enough, two ADCs can share one

LVDS stream, in this way lowering the power consumption devoted to the interface. The unused outputs will

output zero. To avoid consumption from those outputs, no termination should be connected to them. The

distribution on the used output pairs is done in the following way:

• Channel 1 and channel 2 come out on channel 3. Channel 1 comes out first.

• Channel 3 and channel 4 come out on channel 4. Channel 3 comes out first.

• Channel 5 and channel 6 come out on channel 5. Channel 5 comes out first.

• Channel 7 and channel 8 come out on channel 6. Channel 7 comes out first

CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]

Setting this bit to 1 enables the subtraction of the value on the corresponding OFFSET_CHx<9:0> (offset for

channel i) from the ADC output. The number is specified in 2s-complement format. For example,

OFFSET_CHx<9:0> = 11 1000 0000 means subtract –128. For OFFSET_CHx<9:0> = 00 0111 1111 the effect is

to subtract 127. In effect, both addition and subtraction can be performed. Note that the offset is applied before

the digital gain (see DIGITAL_GAIN_ENABLE). The whole data path is 2s-complement throughout internally, with

digital gain being the last step. Only when ADC_OUTPUT_FORMAT = 1 (straight binary output format) is the 2s-

complement word translated into offset binary at the end.

SERIALIZED_DATA_RATE: Address: 3[14:13]

Please see Table 1 for detail description.

Product Folder Links: AFE5808