Datasheet

t
1
t
2
t
3
Device Ready for
Serial Register Write
Device Ready for
Data Conversion
Start of Clock
AVDD
AVDD_5V
AVDD_ADC
DVDD
RESET
SEN
CLKP_ADC
t
4
t
7
t
8
t
6
t
5
AFE5808
www.ti.com SLOS688C –SEPTEMBER 2010–REVISED APRIL 2012
10µs < t
1
< 50ms, 10µs < t
2
< 50ms, –10ms < t
3
< 10ms, t
4
> 10ms, t
5
> 100ns, t
6
> 100ns, t
7
> 10ms,
and t
8
> 100µs.
The AVDDx and DVDD power-on sequence does not matter as long as –10 ms < t
3
< 10 ms. Similar considerations
apply while shutting down the device.
Figure 61. Recommended Power-up Sequencing and Reset Timing
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