Datasheet

AFE5808
www.ti.com SLOS688C –SEPTEMBER 2010–REVISED APRIL 2012
TIMING CHARACTERISTICS
(1)
Typical values are at 25°C, AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V, Differential clock, C
LOAD
=
5pF, R
LOAD
= 100Ω, 14Bit, sample rate = 65MSPS, unless otherwise noted. Minimum and maximum values are across the full
temperature range T
MIN
= 0°C to T
MAX
= 85°C with AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
The delay in time between the rising edge of the input sampling
ta Aperture delay 0.7 3 ns
clock and the actual time at which the sampling occurs
Aperture delay Across channels within the same device ±150 ps
matching
t
j
Aperture jitter 450 Fs rms
Input
ADC latency Default, after reset, or / 0 x 2 [12] = 1,LOW_LATENCY = 1 11/8 clock
cycles
t
delay
Data and frame clock Input clock rising edge (zero cross) to frame clock rising edge (zero 3 5.4 7 ns
delay cross) minus 3/7 of the input clock period (T).
Δt
delay
Delay variation At fixed supply and 20°C T difference. Device to device –1 1 ns
t
RISE
Data rise time Data fall Rise time measured from –100mV to 100mV Fall time measured 0.14 ns
time from 100mV to –100mV 10MHz < f
CLKIN
< 65MHz
t
FALL
0.15
t
FCLKRISE
Frame clock rise time Rise time measured from –100mV to 100mV Fall time measured 0.14 ns
Frame clock fall time from 100mV to –100mV 10MHz < f
CLKIN
< 65MHz
t
FCLKFALL
0.15
Frame clock duty cycle Zero crossing of the rising edge to zero crossing of the falling edge 48% 50% 52%
t
DCLKRISE
Bit clock rise time Bit Rise time measured from –100mV to 100mV Fall time measured 0.13 ns
clock fall time from 100mV to –100mV 10MHz < f
CLKIN
< 65MHz
t
DCLKFALL
0.12
Zero crossing of the rising edge to zero crossing of the falling edge
Bit clock duty cycle 46% 54%
10MHz < f
CLKIN
< 65MHz
(1) Timing parameters are specified by design and characterization; not production tested.
OUTPUT INTERFACE TIMING
(1)(2)(3)
Setup Time (t
su
), ns Hold Time (t
h
), ns
t
PROG
= (3/7)x T + t
delay
, ns
(for output data and frame clock) (for output data and frame clock)
f
CLKIN
,
Input Clock
Input Clock Zero-Cross (rising edge)
Data Valid to Input Clock Zero- Input Clock Zero-Crossing to Data
Frequency
to Frame Clock Zero-Cross (rising
Crossing Invalid
edge)
MHz MIN TYP MAX MIN TYP MAX MIN TYP MAX
65 0.24 0.37 0.24 0.38 11 12 12.5
50 0.41 0.54 0.46 0.57 13 13.9 14.4
40 0.55 0.70 0.61 0.73 15 16 16.7
30 0.87 1.10 0.94 1.1 18.5 19.5 20.1
20 1.30 1.56 1.46 1.6 25.7 26.7 27.3
(1) FCLK timing is the same as for the output data lines. It has the same relation to DCLK as the data pins. Setup and hold are the same
for the data and the frame clock.
(2) Data valid is logic HIGH = +100 mV and logic LOW = -100 mV
(3) Timing parameters are specified by design and characterization; not production tested.
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